The following is about 2 weeks worth of internet searching and chinese translating on Google's part. All of these are taken from various websites, and are not proven to be correct by myself. If any changes need to be made, let me know.
Hope this helps you out!!
Exit Setup Shutdown: Mode 1, Mode 2
Mode 1: when the system boots-up, it will run a little “diagnose”. If the CPU frequency doesn’t change too much, it will skip the “shutdown” function and rewrite the clock generator directly.
Mode 2: no matter how little the clock or DRAM’s ratio has been changed, the system will still “shutdown” and reboot by itself.
Clock VCO Divider: Auto, 2-4
This function is use to fix the clock generator’s divider and “NB Strap” by its jumper. Then, the system wouldn’t reboot again because it presumed itself is not in an overclock status. (This function needs to cooperate with particular FSB jumpers on the mobo)
CPU Clock Ratio:
Also known as the CPU Multiplier
CPU Clock:
FSB Speed
Boot-up clock:
This function can help you out by setting a lower boot up clock as a buffer, when your FSB is tweaked too high in the beginning. The system will boot up with “Boot-up clock” first, after that it will change to your highest FSB.
DRAM Speed:
Auto, 200/667, 200/800, 266/667, 266/800, 266/1066, 333/667, 333/800, 333/1066.
PCIE Clock: Quoted from Anandtech on the DFI UT P35-T2R, but also applied to this board: "Overclocking the PCIE bus can be useful for benchmarking, bringing small gains to overall scores. Unfortunately the P35/ICH9R combo does not have the potential for overall MHz we find with NVIDIA's 680i chipset which could run PCIE frequencies in excess of 150MHz for benchmarking. We also found that overclocking the PCIE bus frequency within the limits of the board exhibited a peculiar issue: the BIOS would revert the bus to x1 PCIE mode for the graphics card between reboots. We managed to get around this by loading optimized defaults every time it occurred and then reloading the overclocked profile we were working on, from a saved CMOS bank. Using the Intel SATA ports, expect around 115MHz to be the maximum. Those wishing to explore PCIE frequencies in excess of 115MHz for benchmarking are advised to use the JMicron controller; we have seen examples of up to 125MHz using this method".
Thermal Management Control: Normally defaults to a shutdown temperature of 85C. Even when overclocking the CPU should never reach this temperature. No effect on 24/7 overclocking.
PPM(EIST) Mode: Enhanced Intel SpeedStep Technology. Allows the operating system, through ACPI, to alter the voltage and frequency of the CPU based on load. Usually no effect on 24/7 overclocking.
Limit CPUID MaxVal: When enabled, sets the CPUID Max Value to 3 for compatibility with older operating systems. Must be disabled for XP and Vista.
CIE Function: Similar to EIST except there are only two possible states for CPU voltage and speed. 1 - The set VCORE and multiplier as configured in the BIOS. 2 - At idle the lowest valid multiplier for the CPU and a reduced percentage of the set VCORE. Usually no effect on 24/7 overclocking.
Execute Disable Bit: Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation. Usually no effect on 24/7 overclocking.
Virtualization Technology: Offers improvements to traditional software-based virtualization solutions. If not using virtualization software there is no need to enable this. Usually no effect on 24/7 overclocking.
Core Multi-Processing: Disables the second die of a quad-core CPU. Regardless of processor this should be set to enabled for 24/7 use.
CPU VID Special Add: Adds to the pre-established vcore in .0125 volt increments, up to .7875 volts (787.5 mV) can be added.
DRAM Voltage Control: The memory voltage regulator, set up in the range between 1.800 V to 3.040V, in 0.025 V increments.
SB Core / CPU PLL Voltage - namely, the South Bridge and CPU frequency control voltage of 1.5 V default, adjusting the ceiling more than 2 V. An increase of this voltage can improve the stability of a high FSB and ensure that the I/O functions remain normal.
NB Core Voltage: Northbridge core voltage can be set up to a maximum of 1.9V
A high FSB of 500 MHz might usually need between 1.35 to 1.4 V, or possibly more.
A 550MHz FSB may need more than 1.5 V, but this is probably the limit and rarely used.
CPU VTT FSB Voltage. CPU VTT voltage regulator options are more important adjustment parameters for the regulation of the P35 chipset of the processor bus voltage. Default VTT voltage is 1.1V, maximum 1.60 V.
Clockgen Voltage Control Its significance lies in the frequency band can effectively reduce noise and provide a more precise locking frequency, possibly making for more stable overclocking. Clockgen Voltage Control is the actual Clockgen IC voltage, and adding this voltage may help increase the stability of a high FSB.
Enhance Data Transmitting: DFI specifically designed a “fine-tune mode” for DATA transmitting performance, Normal for lowest performance, Fast for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.
Enhance Addressing: DFI specifically designed a “fine-tune mode” for DATA addressing, “Normal” for lowest performance, “Fast” for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.
T2 Dispatch: Command Rate (1T, 2T)
CLK fine delay: (there are channel 1,2 in current bios, it going to separate to be 4 items for DIMM1~DIMM4 in upcoming BIOS):
Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output phase forward or backward to create a better match with current DATA operating phase.
The BIOS will automatically calculate a parameter after system boot up.( The latest update BIOS will show the current value of this parameter.)
The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value.
Performance level: It is tRD of DRAM parameter
Read delay phase adjust: It is the fine-tune feature for tRD
MCH ODT Latency: DRAM ODT read/Write latency. Basically ODT is On Die Termination, it likes a variable resistor termination to protect DATA signal integrity from high frequency interference.
Additional Setting Ranges:
MCH ODT Latency: ODT (On Die Termination) is used to match the MCH output impedance to the termination resistance of the RAM. Use of 1-2 is fine in most cases. Even for 4GB overclocking we did not find that more than a setting of 1 was required.
Write to PRE Delay (tWR): Quote from Anandtech: "Range is from 10-13. For high RAM speed, use 12 and above for stability; for benchmarking 10-12 will be faster. Lower is faster."
Rank Write to Read (tWTR): Quote from Anandtech- "Range is 9-11. Use 11 for stability and 10 or 9 for benchmarking. Lower is faster."
ACT to ACT Delay (tRRD): Range is 2-5. 3 is a good setting that allows high enough FSBs for most users. Higher numbers result in less memory read performance.
Read to Write Delay (tRDWR): Range is 8-9. 8 is ideal for most users; higher values are slower.
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Quote from Anandtech: "The ranges for all these settings are quite well manipulated by SPD and BIOS. For those wishing to experiment, 4 is the lowest and most aggressive setting. 5-4-5 may work for SuperPi type benching. There is a slight write/copy speed increase with tighter settings, but this is only useful for the extracting the last ounce of performance. For stability these are best left on AUTO"
Read CAS# Precharge (tRTP): Quote from Anandtech: 2-3 works well on this board for most users. 2 is used for benchmarking while 3 and upwards are best for stability.
ALL PRE to Refresh: Quote from Anandtech: "Range is 4-5. 4 works fine with quad-core CPUs all the way to 475 FSB. A setting of 4 is fine for most benchmarking, unless shooting high over 500FSB."