A Few Notes On Intels Nehalem
"Imitation is the sincerest form of flattery," goes the cliche. If so, then AMD must be feeling mighty flattered, because its deadly rival Intel is set to basically copy two of its most distinctive basic design features: The direct interconnection between the CPU and the motherboard's core logic and an on-die memory controller.
Nehalem is the codename assigned to Intel's intended successor to the wildly successful Core microarchitecture. Its most distinctive design features ape hitherto AMD K8-era (and beyond) exclusives. One of these is the CPU-to-motherboard interconnection technology: Nehalem will be the first-ever Intel CPU to not use a Front Side Bus to communicate with the rest of the system. Instead, as a tacit nod to the elegance of AMD's original Hammer concept, it will feature Intel's answer to the HyperTransport point-to-point link, QuickPath Interconnect (aka simply "QuickPath").
Nehalem will also be the first Intel CPU to feature an on-die memory controller. Again, this is basically a straight lift from AMD's playbook. The IMC (Integrated Memory Controller) has been one of AMD's greatest specific advantages over any Intel design as it allows super-quick access to data stored in RAM. Combined with HyperTransport technology, this meant that raw clock speed scaling remained the only weakness of AMD CPU design compared to Intel.
I think it's a great leap forward for Intel to copy AMD's best features. Compared to the HyperTransport link, the Front Side Bus is less efficient at transporting data. This is one reason why Intel CPUs tend to have much larger L2 (and now L3) caches compared to the contemporary AMD offering. Secondary and tertiary caches store data instead of in the RAM, which would need to travel through the FSB to the CPU. Increased cache sizes and faster FSBs mitigated against this inherent handicap compared to AMD's implementation of the HT Link (aka LDT, or Lightning Data Transport; don't you just love marketing-speak?), but carried penalties such as larger power demands and latency.
In the NetBurst era, Intel tried a brute force solution to the problems introduced by AMD K8's more elegant design: They tried to just ramp up the clock speeds to make up for the much slower RAM access times (the shortness of the P4's instructional pipelines didn't help either). There was just no hope with this kind of solution; think of a small-capacity motorcycle engine that's capable of massive RPMs trying to produce the same power and torque outputs of a even a medium-capacity V6 or V8 automobile engine running far fewer revs. Intel's designers came up against two limits: One was the thermal dissipation of the fastest NetBurst cores, and consequently, the proverbial "rev limit" of the existing designs. Intel had bragged (and hoped for) a Pentium 4 that could scale to maybe 5GHz and beyond (some sources indicate they hoped for a hyperbolic 10GHz), but this simply wasn't possible.
To its credit, Intel used its massive resources and admitted that NetBurst technology had reached its pragmatic limits. This marked the advent of the Core microarchitecture, and it is the foundation of Intel's renaissance as the pre-eminent producer of CPUs.
Nehalem is similarly a wise investment on Intel's part, in that it learned that there is more than one path to performance. By doing away with the Front Side Bus entirely, Intel sheds Core's only true weakness: In terms of data transfer speed, the FSB is still slower and less efficient than HyperTransport is. A point-to-point trip simply is just quicker than taking the scenic route.
But one cannot help but smile when you stop and think about how Goliath learned such a great lesson from David in this instance. Not that there's anything wrong with that, per se; a great lesson is still a great lesson.
Thank you for your time and consideration. Comments and discussion are always most welcome!
Nehalem is the codename assigned to Intel's intended successor to the wildly successful Core microarchitecture. Its most distinctive design features ape hitherto AMD K8-era (and beyond) exclusives. One of these is the CPU-to-motherboard interconnection technology: Nehalem will be the first-ever Intel CPU to not use a Front Side Bus to communicate with the rest of the system. Instead, as a tacit nod to the elegance of AMD's original Hammer concept, it will feature Intel's answer to the HyperTransport point-to-point link, QuickPath Interconnect (aka simply "QuickPath").
Nehalem will also be the first Intel CPU to feature an on-die memory controller. Again, this is basically a straight lift from AMD's playbook. The IMC (Integrated Memory Controller) has been one of AMD's greatest specific advantages over any Intel design as it allows super-quick access to data stored in RAM. Combined with HyperTransport technology, this meant that raw clock speed scaling remained the only weakness of AMD CPU design compared to Intel.
I think it's a great leap forward for Intel to copy AMD's best features. Compared to the HyperTransport link, the Front Side Bus is less efficient at transporting data. This is one reason why Intel CPUs tend to have much larger L2 (and now L3) caches compared to the contemporary AMD offering. Secondary and tertiary caches store data instead of in the RAM, which would need to travel through the FSB to the CPU. Increased cache sizes and faster FSBs mitigated against this inherent handicap compared to AMD's implementation of the HT Link (aka LDT, or Lightning Data Transport; don't you just love marketing-speak?), but carried penalties such as larger power demands and latency.
In the NetBurst era, Intel tried a brute force solution to the problems introduced by AMD K8's more elegant design: They tried to just ramp up the clock speeds to make up for the much slower RAM access times (the shortness of the P4's instructional pipelines didn't help either). There was just no hope with this kind of solution; think of a small-capacity motorcycle engine that's capable of massive RPMs trying to produce the same power and torque outputs of a even a medium-capacity V6 or V8 automobile engine running far fewer revs. Intel's designers came up against two limits: One was the thermal dissipation of the fastest NetBurst cores, and consequently, the proverbial "rev limit" of the existing designs. Intel had bragged (and hoped for) a Pentium 4 that could scale to maybe 5GHz and beyond (some sources indicate they hoped for a hyperbolic 10GHz), but this simply wasn't possible.
To its credit, Intel used its massive resources and admitted that NetBurst technology had reached its pragmatic limits. This marked the advent of the Core microarchitecture, and it is the foundation of Intel's renaissance as the pre-eminent producer of CPUs.
Nehalem is similarly a wise investment on Intel's part, in that it learned that there is more than one path to performance. By doing away with the Front Side Bus entirely, Intel sheds Core's only true weakness: In terms of data transfer speed, the FSB is still slower and less efficient than HyperTransport is. A point-to-point trip simply is just quicker than taking the scenic route.
But one cannot help but smile when you stop and think about how Goliath learned such a great lesson from David in this instance. Not that there's anything wrong with that, per se; a great lesson is still a great lesson.
Thank you for your time and consideration. Comments and discussion are always most welcome!
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