Verilog Testbench -

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post #1 of 1 Old 03-04-2008, 02:14 PM - Thread Starter
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I was wondering if anybody had experience with the Verilog hardware programming. Its an HDL, different then regular. But for class i built a 32-bit ALU and now i have to create a test bench putting through a series of tests. I have to read the test vectors in from a file. i was having trouble setting this up. If need be i can post what i have if anybody could help.

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