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Old 02-12-09   #1 (permalink)
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Default D Flop question
I'm workin on something for a piece of hardware, say if I have the D and clock both going from low to high on the positive rising edge of the clock, will Q immediately go high as well or will there be a delay, and it will only go high on the next rising edge?

for reference I'm using http://web.mit.edu/6.111/www/s2008/d...ets/74LS74.pdf for the chip
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Old 02-12-09   #2 (permalink)
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nvm answered it myself
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Old 02-13-09   #3 (permalink)
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Well. what was your answer??
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