[ShGr] Intel Atom Z550 2.0GHz tipped as imminent - Page 4 - Overclock.net

lordikon · 03-20-09

Quote:

Originally Posted by Ben the OCer

Yes that is what we are saying because it's true. The biggest reason for this is the super high 20 stage pipeline of Willamette and Northwood. For Prescott Intel increased it again to an astonishing 31 stage pipeline. This is why Northwood is faster clock for clock than Prescott in cases where the extra L2 cache doesn't overcome the higher stage pipeline. The P3 has only a 10 stage pipeline.

Yes, but the P3 also didn't use any SSE2 or SSE3 instruction sets.

skugpezz · 03-20-09

Quote:

Originally Posted by AMD+nVidia

My Atom is 1.86GHz dual core with hyper threading. This isn't the same?

yours is single core hyper threading

Coma · 03-20-09

Quote:

Originally Posted by Takendown2

Here you go, P3 is faster clock for clock VS P4s... and these Atoms are around the speed of a p4 clock for clock

That doesn't look like faster for me, that looks like optimized. If it were faster, it would ALWAYS be faster. The fact it's only faster in some programs means those were optimized for P3s, but not for P4s.

If you used a simple benchmark with an operation that isn't optimized for either, the P4 would come out on top.

AMD+nVidia · 03-20-09

Quote:

Originally Posted by skugpezz

yours is single core hyper threading

No.. it is most definitely a dual. I see 4 cores in Windows.

2 + 2 = 4

darksideleader · 03-20-09

Quote:

Originally Posted by the_milk_man

Why is no one talking about the 3.33GHz i7!!?? I wanna hear more about the i7!!!

because we'd rather go down memory lane and talk about P3 vs. P4

Tator Tot · 03-20-09

Quote:

Originally Posted by darksideleader

because we'd rather go down memory lane and talk about P3 vs. P4

More likes Atom's are just so much cooler.

The amount of performance perwatt, small package. And its just overall sex apeal...mmm...silicon sex appeal.

Cheetos316 · 03-20-09

Let's get the facts straight with this whole Pentium 3 (codenamed P6) vs. Pentium 4 (we'lll call P4) architecture debate:

From an architectural point of view, the P6 architecture is much more efficient than that of the P4. From the beginning, the Pentium 4 architecture was designed with the primary goal of raising clockspeed, simply because the consumer only knew about clockspeed at the time thus CPUs designed to achieve very high clockspeeds will equal much more profit. This was the time of the clockspeed race and Intel wanted something that would assure them the win. The P4 architecture took the existing P6 architecture and narrowed it from a 3-issue core to a 2-issue core and then took the 16 stage pipeline and lengthened it all the way to 31 stages (Prescott). Because each stage of the 16 stage pipeline was basically divided into two, that meant that the clockspeed has just been doubled, but to do the same amount of work.

In doing so, there were a couple of major disadvantages:

The first is power consumption. When running the core at that speed, the transistors of Intel's silicon became very leaky, leading to extremely high power consumption numbers (which then required more powerful cooling methods). If we compare a P6 CPU to a P4 CPU that does the same amount of work in the same time, the P4 CPU would have to operate at a higher clockspeed and because of the leaky transistors, would consume much more power, and all for doing the same amount of work. In order to outperform the P6 chips, even higher clockspeeds were used and the power consumption and transistor leakage increased not linearly, but exponentially.

Then, there is the flow of data of the pipelines. Remember that the memory controller was located on the northbridge and ran at a much much lower clockspeed, leading to much more idle stages. Hyperthreading was used in an effort to recoup the lost idle stages, but it required more die space. And because of the extremely long pipeline, it is much harder for the branch predictors to predict that far down the pipeline, leading to even more misses and stalls.

Of course there were cases in which the super long pipeline performed better than the shorter pipeline, but only under a small number of cases. And yes the P4 did have the newer SSE instructions, but very few applications took advantage of those instructions.

Arstechnica has a couple of in-depth articles covering the details of the architectures for those who want to reference them:

The future of Prescott: when Moore gives you lemons

The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II)

bomfunk · 03-20-09

Quote:

Originally Posted by Cheetos316

Let's get the facts straight with this whole Pentium 3 (codenamed P6) vs. Pentium 4 (we'lll call P4) architecture debate:

From an architectural point of view, the P6 architecture is much more efficient than that of the P4. From the beginning, the Pentium 4 architecture was designed with the primary goal of raising clockspeed, simply because the consumer only knew about clockspeed at the time thus CPUs designed to achieve very high clockspeeds will equal much more profit. This was the time of the clockspeed race and Intel wanted something that would assure them the win. The P4 architecture took the existing P6 architecture and narrowed it from a 3-issue core to a 2-issue core and then took the 16 stage pipeline and lengthened it all the way to 31 stages (Prescott). Because each stage of the 16 stage pipeline was basically divided into two, that meant that the clockspeed has just been doubled, but to do the same amount of work.

In doing so, there were a couple of major disadvantages:

The first is power consumption. When running the core at that speed, the transistors of Intel's silicon became very leaky, leading to extremely high power consumption numbers (which then required more powerful cooling methods). If we compare a P6 CPU to a P4 CPU that does the same amount of work in the same time, the P4 CPU would have to operate at a higher clockspeed and because of the leaky transistors, would consume much more power, and all for doing the same amount of work. In order to outperform the P6 chips, even higher clockspeeds were used and the power consumption and transistor leakage increased not linearly, but exponentially.

Then, there is the flow of data of the pipelines. Remember that the memory controller was located on the northbridge and ran at a much much lower clockspeed, leading to much more idle stages. Hyperthreading was used in an effort to recoup the lost idle stages, but it required more die space. And because of the extremely long pipeline, it is much harder for the branch predictors to predict that far down the pipeline, leading to even more misses and stalls.

Of course there were cases in which the super long pipeline performed better than the shorter pipeline, but only under a small number of cases. And yes the P4 did have the newer SSE instructions, but very few applications took advantage of those instructions.

Arstechnica has a couple of in-depth articles covering the details of the architectures for those who want to reference them:

The future of Prescott: when Moore gives you lemons

The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II)

Hi, it's bomfunk, the professional nitpicker

First, P3 had 10 pipeline stages, not 16. Northwood and Williamette had both 20 and prescott had 31.

Next... well, you're right. No comments. Spot on

D

P6 was by nature more efficient than NetBurst, but CPU-specific optimizations paired up with new iterations of SSE gave new P4s (Northwood, Prescott) a significant advantage. However, when running code not optimized for any specific CPU architecture, NetBurst would get thrashed thanks to its common pipeline stalls.

dasparx · 03-20-09

Quote:

Originally Posted by bomfunk

Hi, it's bomfunk, the professional nitpicker

First, P3 had 10 pipeline stages, not 16. Northwood and Williamette had both 20 and prescott had 31.

Next... well, you're right. No comments. Spot on

D

P6 was by nature more efficient than NetBurst, but CPU-specific optimizations paired up with new iterations of SSE gave new P4s (Northwood, Prescott) a significant advantage. However, when running code not optimized for any specific CPU architecture, NetBurst would get thrashed thanks to its common pipeline stalls.

That's why i kept my Tualatin P3 @ 1.55Ghz (Water)(, wich sadly does ~1400 now

) until the Athlon64 days, it was fast enough for me.
Still got it as reserve sys, paired with an GF6600

PiratesRule · 03-20-09

When is a more efficient chipset coming out?

I'll be interested then...

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[ShGr] Intel Atom Z550 2.0GHz tipped as imminent

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