C2D and Quad Temp guide by Computronix - Page 6 - Overclock.net

GigaByte · 03-08-08

Quote:

Originally Posted by opt33

http://eda-publishing.imag.fr/spip/IMG/pdf/TMI23.pdf
If this one gets taken down from too much traffic as well, just search the title of article in above post.

Yes, a lot has, the gradient has gotten even less than (.4C as measured by hardware, no software errors there). It is now probably less. See intels prediction model.
http://www.flomerics.com/flotherm/te...apers/t324.pdf

Not according to the intel engineers that designed the chip.
http://eda-publishing.imag.fr/spip/IMG/pdf/TMI23.pdf
"It can be seen that large temperature gradients exist on the die (max was 5.2C). It also can be noted that some workloads display high temperature gradients while others have no offset. Thermal control algorithms need to prevent the hot spot from exceeding the max temperature specification.

Yes, but only by ~1C in modern cpus at idle.

This statement is based on circular reasoning, and gets to the point of the disagreement. When DTS=0, and accurate temp probe or IR gun on Tcase of my E8400 temp reads 94.5C. You will claim a gradient exists of 10C (though you dont know that, unkown1, unless tjmax is 105C), thus proving tjmax is 105. Or you will claim tjmax is 105 (though you dont know that, unknown2 unless gradient is 10C), thus they have a gradient of 10C. I am saying gradient (unkown 1) is only 1C from intel documents and experiments above , and tjmax (unkown 2, but can know be solved for if gradient is 1C) is ~95C.

Without knowing the gradient or tjmax, 2 unkowns, you are using circular reasoning. Or you are saying mobile cpus have the same tjmax as desktops, though intel has said that is incorrect multiple times, and have even explained why based on thermal resistance differences. Or you have directly measured the gradient (drilling a hole in your cpu is required) or can point to a source that has. I have evidence directly from intel in links above that support my argument of the gradient being less than 1C at idle, thus tjmax is ~95-96. Now, here is the question, where is your evidence of claiming a gradient exists of 10-15C, (and please no more circular reasoning with two unkowns, tjmax and gradient)?

All I will say is please re-read the WHOLE guide, and do the verification tests yourself. There is no current CPUs with Tj max of 95c, let alone 96c. There is only 85c, 100c and 105c. Iam sorry but what you are saying is not correct.

Crrust · 03-08-08

Quote:

This statement is based on circular reasoning, and gets to the point of the disagreement. When DTS=0, using an accurate temp probe or IR gun, Tcase of my E8400 is 94.5C. You will claim a gradient (unknown1) exists of 10C (though you dont know that, unless tjmax is 105C), thus proving tjmax (unknown2) is 105C. Or you will claim tjmax is 105 (though you dont know that, unless gradient is 10C), thus they have a gradient of 10C, and back to 105C Tjmax. I am saying gradient (unkown 1) is only 1C from intel documents, ie I solved for one unknown, and experiments above , and tjmax (unkown 2, but can know be solved for if gradient is 1C) is ~95C.

Without knowing the gradient or tjmax, 2 unkowns, you are using circular reasoning. Or you are saying mobile cpus have the same tjmax as desktops, though intel has said that is incorrect multiple times, and have even explained why based on thermal resistance differences. Or you have directly measured the gradient (drilling a hole in your cpu is required) or can point to a source that has. I have evidence directly from intel in links above that support my argument of the gradient being less than 1C at idle, thus tjmax is ~95-96.

Now, here is the question, where is your evidence of claiming a gradient exists of 10-15C, (and please no more circular reasoning with two unkowns, tjmax and gradient)?

I, and the guide, am saying that TjunctionMax = the point at which thermal shutdown occurs. This can easily be verified by pushing a chip to this point. This has nothing to do with the delta between Tcase and Tjunction. In all honesty by the time you reach TjunctionMax you, according to Intel, have already put your chip under conditions which can damage it by exceeding TcaseMax. TcaseMax is specified by Intel as the Thermal Specification for each chip. For an E8400 it is 72.3°C.

If you are brave enough to risk your processor then I say test it yourself =) I am 100% certain that you will find that at TjunctionMax -5°C (100°C) your processor will begin throttling. If it continues to heat up past this to a temperature of 105°C it will shutdown, thus providing us with the TjunctionMax.

Reading the article on Thermal Measurement it is not relating to the delta that is discussed in this temperature guide. It is relating specifically to the temperature gradient on the die of the processor itself. If you read the guide you will see that each core has an embedded DTS that reads the specific core temperature and a diode under ISH at the geometric center of the cores. The delta, or gradient, that we are talking about is the difference between these two temperature readings. What you seem to be talking about is a gradient in the Tjunction reading itself. If this is indeed what you are talking about, and certainly what the article is talking about, then I would agree that a gradient of 0.4°C seems reasonable.

opt33 · 03-08-08

Quote:

Originally Posted by Crrust

I, and the guide, am saying that TjunctionMax = the point at which thermal shutdown occurs. This can easily be verified by pushing a chip to this point. This has nothing to do with the delta between Tcase and Tjunction. In all honesty by the time you reach TjunctionMax you, according to Intel, have already put your chip under conditions which can damage it by exceeding TcaseMax. TcaseMax is specified by Intel as the Thermal Specification for each chip. For an E8400 it is 72.3°C.

If you are brave enough to risk your processor then I say test it yourself =) I am 100% certain that you will find that at TjunctionMax -5°C (100°C) your processor will begin throttling. If it continues to heat up past this to a temperature of 105°C it will shutdown, thus providing us with the TjunctionMax.

Reading the article on Thermal Measurement it is not relating to the delta that is discussed in this temperature guide. It is relating specifically to the temperature gradient on the die of the processor itself. If you read the guide you will see that each core has an embedded DTS that reads the specific core temperature and a diode under ISH at the geometric center of the cores. The delta, or gradient, that we are talking about is the difference between these two temperature readings. What you seem to be talking about is a gradient in the Tjunction reading itself. If this is indeed what you are talking about, and certainly what the article is talking about, then I would agree that a gradient of 0.4°C seems reasonable.

Have already done this. My cpu begins throttling at around 92C-93C Tcase and at 94.5C DTS=0. I am saying gradient is ~1c or less (thus tcase is measuring core to within 1C) and therefore, tjmax on my E8400 is 95.5C. Another on xtremesystems has done the same and concluded also his tjmax is 95C.

Edit: here is another way of illustrating my point. Using incorrect tjmax of 105, coretemp reads my temps incorrectly at 99C (~10C to high) when IR gun (calibrated to +/- 1C) is measuring Tcase as 87.8C. However, if I change tjmax to a more accurate value of 95, then coretemp would read correctly 89C when Tcase is 87.8C. (see pic, sorry blurry on IR, hard to get, but if you stare at pic long enough, you can make out numbers, it scales 10C off all the way from 50C to 105C, using tjmax of 105.)

Crrust · 03-08-08

Updated the temp guide with the latest revision February 2008. A lot of new information.

Crrust · 03-08-08

Quote:

Originally Posted by opt33

Have already done this. My cpu begins throttling at around 92C-93C Tcase and at 94.5C DTS=0. I am saying gradient is ~1c or less (thus tcase is measuring core to within 1C) and therefore, tjmax on my E8400 is 95.5C. Another on xtremesystems has done the same and concluded also his tjmax is 95C.

Hmm...I will mull this over tonight and get back to you tomorrow. I am not sure what to make of what you are telling me. It goes against all previous testing with C2D and Quad chips to date that I know of. Need time to process =)

opt33 · 03-08-08

Quote:

Originally Posted by Crrust

Hmm...I will mull this over tonight and get back to you tomorrow. I am not sure what to make of what you are telling me. It goes against all previous testing with C2D and Quad chips to date that I know of. Need time to process =)

I added a pic to my post for clarification.

Crrust · 03-09-08

OK, I slept on it and have a few questions for you for clarification:

1. Can you explain your test method? I am looking at the picture you posted and I see 99°C displayed by CoreTemp, and 87.8°C displayed by what? Details of the test conditions would be helpful too so that I can wrap my brain around this.

2. What software are you using to check your temperatures, in particular, your Tcase temperature?

3. Have you ensured that your temperatures are calibrated to verify accuracy?

To be honest, after looking at that picture, I am not sure I understand your earlier post. You were saying earlier that you experienced TjunctionMax for your chip at 94.5°C, but in the photo CoreTemp is displaying a core temperature of 99°C and you are still running.

I am also wondering about the 87.8°C displayed. Is that a temperature probe that you are using to measure Tcase temps? If so, I am very skeptical that you can achieve an accurate Tcase reading using any type of external probe. Tcase is measured at the geometric center between the cores, under the IHS. In my opinion the only accurate way, outside of laboratory conditions, to measure Tcase is with software displaying the temperature read by the Thermal Diode under the IHS. Anyway, my thoughts so far this morning.

I am genuinely interested in getting to the bottom of this so please keep up the discussion =)

opt33 · 03-09-08

Quote:

1. Can you explain your test method? I am looking at the picture you posted and I see 99°C displayed by CoreTemp, and 87.8°C displayed by what? Details of the test conditions would be helpful too so that I can wrap my brain around this.

I have used an IR gun to back of IHS of cpu (picture). I have double checked it with an accurate temp probe from my wifes work, was within .5C. Yes coretemp reads 99C, and it is wrong, because tjmax is wrong on coretemp. Displayed coretemp = Tjmax (guessed by coretemp from mobile cpus as 105) - DTS (accurately read from chip).
99C is displayed because 105-6 = 99. However substitute the correct tjmax of 95, now 95-6=89C. Of course I am still going, because core temp is ~89C, coretemp is wrong b/c using wrong tjmax.

Quote:

2. What software are you using to check your temperatures, in particular, your Tcase temperature?

No software, direct temp probe or IR gun to Tcase.

Quote:

3. Have you ensured that your temperatures are calibrated to verify accuracy?

yes IR gun +/- 1C, Temp probe accurate to .3c, two reading within .5c each other. Another person on xtreme, got same 95C measurement.

Quote:

To be honest, after looking at that picture, I am not sure I understand your earlier post. You were saying earlier that you experienced TjunctionMax for your chip at 94.5°C, but in the photo CoreTemp is displaying a core temperature of 99°C and you are still running.

Of course it is still going, coretemp is reading 10C high, because tjmax is set 10c high. If tjmax were correctly set to 95C, then coretemp would read the temp correctly at 89C.

Quote:

I am also wondering about the 87.8°C displayed. Is that a temperature probe that you are using to measure Tcase temps? If so, I am very skeptical that you can achieve an accurate Tcase reading using any type of external probe. Tcase is measured at the geometric center between the cores, under the IHS.

No, Tcase is measured in geometric center of IHS, exactly as I and others are doing, see attached pics from intel on how to measure, side and top down views. The gradient across the IHS is <0.1C at idle, that is documented in several places, so thats a mute point anyways. The only potential gradient source is TIM1/bond (between core and IHS)...not across IHS. TIM1 is not shown in pic, only TIM2 from heatsink, but TIM2 and heatsink is of course removed for our measurements.
http://download.intel.com/design/pro...x/31873401.pdf

opt33 · 03-09-08

pardon the double post, but just so we are all on same page.

displayed temp = tjmax (guessed at) - DTS (always accurate, read from chip)

You can set tjmax to any fictitious number you want, and it will not change DTS or the temp at which throttling occurs, all it will do is change the guessed at absolute temp when DTS=0, ie throttling occurs.

coretemp example tjmax 105
105 - 6 = 99
105 = tjmax guess by coretemp (based on mobile cpus)
6= DTS, always accurate, read directly from chip, and means I am 6C from throttling, regardless of accurate absolute temp guess from tjmax guess
99=wild guess at absolute temp, because tjmax is wild guess.

speedfan example tjmax 100
100-6=94
100=tjmax guess by speedfan
6=DTS, again always accurately read from chip and shows temp from throttling
94=wild guess at absolute temp, because tjmax is wild guess.

assume tjmax of 95
95-6=89
95=tjmax approximation from measurements at idle
6=DTS, always accurately read, and changing tjmax, thus changing guess at absolute temp, does not alter throttling temp.
89= better guess based on real measurements.

GigaByte · 03-09-08

Crrust can you ask Computroix about 95c Tj max for M0 steppings? Since hes changed it to 85c and a delta of 5c, it just doesn't fit at all. My Tcase is higher than the cores with 85c Tj max and Tcase is calibrated correctly. The only way to get the cores above Tcase within the delta range is to give Tcase a minus temp offset which will put it below ambient, and thats how it don't work. But using with a 95c Tj max the proposed 5c delta fits perfectly, Tcase is untouched, and cores are above Tcase.

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C2D and Quad Temp guide by Computronix

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