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Old 07-14-09   #21 (permalink)
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Well, this guide worked! At 4.0 GHz. now. Still have to run Prime95 for a longer spurt, but as I have a D0, and followed every instruction to the letter, I see no reason why it should fail.
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Old 07-14-09   #22 (permalink)
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Yay! Gratz Beric.

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Old 07-14-09   #23 (permalink)
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Chad, if you run higher bclk's but with a smaller multi would you need to increase the IOH volts? I've just ran a 15 hour small fft Prime run with no probems @ 3.8
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Old 07-14-09   #24 (permalink)
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Congrats. How high? IOH helps to stabilize ram. Are you trying to run like 211x18 or something similar? You're going to probably max out at ~220 on that board.

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Old 07-15-09   #25 (permalink)
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I've left my overclock @ 3.8, i feel it's a good balance between temps/vcore used & power. When i feel the need for some benching or just fooling around, the i'll go higher.

I'm currently @ 200*19, when i go for 4GHz it'l be 211*19. So if i had a stable 4GHz overclock with 200*20, would i need any more volts for 211*19?
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Old 07-15-09   #26 (permalink)
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Maybe, maybe not. Some say the 20x multiplier requires more volts for a stable overclock. I think it depends on your chip and board.

One day I want to graph max stable frequency at every voltage and see if there's any sort of predictability, so that if you knew a few stable frequencies on another chip you could predict exactly where you'd need to go, but I doubt I'll have time for that for a while.

EDIT: I have added more info on prime 95 errors and disabling BSOD restarts.

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Old 07-16-09   #27 (permalink)
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I cannot find the Tj Max in i7 datasheet!! Is 100C as stated in Real Temp correct?

I'm wondering what would the absolute Tj max be.
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The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers.

The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands.

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Old 07-16-09   #28 (permalink)
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The TJ max is 100.

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Old 07-18-09   #29 (permalink)
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Great guide.

I keep getting a 'A Clock interrupt was not received on a secondary processor within the
allocated time interval' BSOD, though at the time I was running at ~1.115 Vcore. Been bumping Vcore and I still get it occasionally. Has that error been attributed to any other voltage?
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Old 07-18-09   #30 (permalink)
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whats the code? Whats your bclk?

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