Memory: Dividers, Latencies, and Bandwidth Explained - Page 4 - Overclock.net

pauldovi · 06-26-07

Quote:

Originally Posted by Litlratt

If I understand this correctly, if both examples were running the same timings, then the latency would be the same.
If you can maintain tight timings and continually increase speed, then performance increases regardless of the divider.

No, the latencies that are incurred upon the memory system is dependent upon the speed of the memory and the timing of the latencies.

Litlratt · 06-26-07

Quote:

Originally Posted by pauldovi

No, the latencies that are incurred upon the memory system is dependent upon the speed of the memory and the timing of the latencies.

This is where I'm confused.
From your guide:
For example:

DDR2-800 does 800,000,000 cycles per second. Latencies of 4-4-4-12 add up to 24 cycles per operation of latency. Divide 24 cycles of latencies by 800,000,000 cycles and you get 30 nano-seconds worth of latencies per operation. However, DDR2-1000 with latencies of 5-5-5-15 also net you the same 30 nano-seconds of latencies per operation (30 / 1,000,000,000).

However, even though both settings have the same latencies. DDR2-1000 @ 5-5-5-15 is better than DDR2-800 @ 4-4-4-12, this is because DDR2-1000 has more data throughput when compared to DDR2-800.

If both examples are at 4 4 4 12 then that's 24 nano seconds regardless of speed. Where/how does the speed of the ram fall into the equation?

Rep+ for spending your time educating us paul. Thank you.

Ihatethedukes · 06-26-07

To further clarify that, the 1066 5-5-5-15 would have significantly lower latencies than the 800 5-5-5-15 all else being equal.

This is an ultra simplistic explanation (READ: total over-simplification) but:

30 clocks of latency is a variable amount of time. Look at it this way, a 'clock' is simply one period of the sine wave that the memory is running on.

If you're running 10Hz with 1 clock of waiting you now have 9 times per second that the ram is DOING stuff.

Now, if you're still running one clock of latency but now have ram running 20Hz, you now have 19 times per second your ram is DOING something.

1 clock of latency/10 clocks per second = 0.1s and 1 clock of latency/20 clocks per second = 0.025

So now your REAL latencies are at the given speeds are 0.1s and .025s, respectively. Theoretically doubling ram speed at the SAME latency will cut your REAL latency times by 75%.

pauldovi · 06-26-07

Quote:

Originally Posted by Litlratt

This is where I'm confused.
From your guide:
For example:

DDR2-800 does 800,000,000 cycles per second. Latencies of 4-4-4-12 add up to 24 cycles per operation of latency. Divide 24 cycles of latencies by 800,000,000 cycles and you get 30 nano-seconds worth of latencies per operation. However, DDR2-1000 with latencies of 5-5-5-15 also net you the same 30 nano-seconds of latencies per operation (30 / 1,000,000,000).

However, even though both settings have the same latencies. DDR2-1000 @ 5-5-5-15 is better than DDR2-800 @ 4-4-4-12, this is because DDR2-1000 has more data throughput when compared to DDR2-800.

If both examples are at 4 4 4 12 then that's 24 nano seconds regardless of speed. Where/how does the speed of the ram fall into the equation?

Rep+ for spending your time educating us paul. Thank you.

Well the example has the DDR2-1000 @ 5-5-5-15 and the DDR2-800 @ 4-4-4-12.

The way you compute latencies per operation is to add up the timings 4+4+4+12 = 24 and then divide by the operations per second (800,000,000)

24 / 800,000,000 = 30 nano seconds of latencies per operation

30 / 1,000,000,000 = 30 nano seconds of latencies per operation

Litlratt · 06-26-07

Quote:

Originally Posted by pauldovi

Well the example has the DDR2-1000 @ 5-5-5-15 and the DDR2-800 @ 4-4-4-12.

The way you compute latencies per operation is to add up the timings 4+4+4+12 = 24 and then divide by the operations per second (800,000,000)

24 / 800,000,000 = 30 nano seconds of latencies per operation

30 / 1,000,000,000 = 30 nano seconds of latencies per operation

I'll try again.
If both speeds of ram are running the same timings, then the faster ram not only has more bandwidth but is also has faster latencies.
So:
If you can maintain tight timings and continually increase speed, then performance increases regardless of the divider.

Ihatethedukes · 06-26-07

You will never get decreased performance from upping a divider ll else equal. However, if you have to choose between maxing your ram on the 3:2 divider and leaving your CPU 200 MHz short of its max and running the 200MHz more on your CPU and losing a 100-200MHz on your ram... ALWAYS pick the CPU speed.

pauldovi · 06-26-07

Quote:

Originally Posted by Litlratt

I'll try again.
If both speeds of ram are running the same timings, then the faster ram not only has more bandwidth but is also has faster latencies.
So:
If you can maintain tight timings and continually increase speed, then performance increases regardless of the divider.

Right.

The divider is just a way of comparing the FSB to the memory speed. It doesn't really mean anything.

Ihatethedukes · 06-26-07

You know, Pauldovi, I've been thinking that the ram latencies are not quite as additive as you say they are. I couldn't put my finger on why until I found this little baby. As you can see, ras and cas latencies overlap and are not directly additive.

http://arstechnica.com/paedia/r/ram_...e.part2-1.html

FrankenPC · 06-26-07

Quote:

Originally Posted by Ihatethedukes

You know, Pauldovi, I've been thinking that the ram latencies are not quite as additive as you say they are. I couldn't put my finger on why until I found this little baby. As you can see, ras and cas latencies overlap and are not directly additive.

Which would imply CAS and tRAC produce the most latency? Am I interpreting that correctly???

Ihatethedukes · 06-26-07

Okay, this explains why tras doesn't matter very much in performance. The other three ratings do. They are the CAS latency, the RAS-to-CAS delay, the RAS precharge time and the Ras active.

If you look at the chart ras is activated and lasts a long time. However, before it is terminated, Cas is already activated (provided your ras active time is set to more than your ras to cas delay) and ras can last through the ras to cas delay PLUS the cas active without any significant detrimental effects to performance because it cannot be reactivated until CAS active is over. It does need to allow time to precharge ras before it can be activated again but that time is small. (3-5 clocks on today's DDR2) On 4-4-4-10 ram ras can be ras to cas delay + cas latency + cas active - ras precharge delay WITHOUT ANY REAL DETRIMENTAL EFFECT TO PERFORMANCE. So, 4+cas active clocks, which is memory serves me correctly is 4-8 bursts. Which makes sense with most ram being ras10.

It would seem that Cas + ras to cas delay introduce the most latency.

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Memory: Dividers, Latencies, and Bandwidth Explained

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