pauldovi

I have seen plenty of thread on this forum with people who are a little confused about the relationship between the processor and the memory, and how latencies and dividers effect memory bandwidth. I hope to answer those questions with this short guide:

Disclaimer: This guide is intended to reference Intel core logic (i.e. 965P / 975X), not Nvidia or ATI chipsets. It should still work out the same, however, some will argue that Nvidia works better in a "synced" state. I cannot discredit this as I simply do not know.

Current systems use DDR, DDR2, and in the future DDR3 memory. DDR stands for dual data rate. What this means is that the memory transmits data on both ends of the sine curve. For those less mathematically inclined, the result is 2 times the data bandwidth. The number after DDR stands for the generation of memory. Newer generations have the capability of higher speeds than older generations, but are no faster at the same speeds. We will focus on DDR2 memory, since that is what is used the majority of current Intel systems (Q2 07).

Your memory speeds can be tricky. This is because, like the CPU's FSB, it has rated and actual speeds.

For example, DDR2-800, is DDR2 memory rated at 800Mhz. However, that is its rated (Dual Data Rate) speed. The memory is actually only running at 400Mhz, but since data is being read on both peaks of each cycle, its rated speed is doubled.

Memory takes data from the system's hard drive and communicates it to the CPU for execution.

People compare the speed of the memory as a ratio to the CPU's FSB. For this ratio, you use the actual memory speed, not the rated speed.

For example, a CPU with a FSB of 266.66Mhz will be in a 1:1 ratio with memory at 266.66Mhz (DDR2-533)

People are confused (misinformed) as to what ratio is optimal for system performance. When looking at the bandwidth in terms of MB/s, your memory needs to be operating 2 times as fast as the CPU's FSB in order to match the CPU's L2 bandwidth. If you want to calculate your CPU’s or memory’s bandwidth you simply multiply the actual frequency by .016. This will give you the maximum theoretical bandwidth in GB/s.

For Example:

DDR2-800 has an actual speed of 400Mhz. 400Mhz x .016 = 6.4GB/s maximum bandwidth.

So, for optimal settings a CPU with a FSB of 266.66Mhz would want memory running at 533Mhz (DDR2-1066). However, this is highly unlikely that you will have memory that can run in a 2:1 ratio with your FSB. A 1:1 ratio is more often the target ratio as it is easier to reach with most memory.

A more in depth (mathematical) way of explaining the memory and system relationship is as follows:

If you want to calculate FSB bandwidth of a Core 2 Duo you multiply bus frequncy (266.66) times the transfers per clock (4) and the FSB width (64bit or 8 byte).

Therefore, a system with a 266.66Mhz FSB (stock Core 2 Duo) has a FSB bandwidth of:

266.66 x 4 x 8 = 8533.33MB/s

Your memory has a 64bit (8 byte) width and a capability of 2 transfers per clock (DDR).

Therefore, to flood the FSB bandwidth you get:

8533.33MB/s = X Mhz * 2 * 8
8533.33MB/s = X Mhz * 16
533.33Mhz = X

Therefore a memory bus speed of 533.33Mhz or DDR2-1066 will flood the FSB bandwidth.

Memory also has a series of latencies. Latencies are measured in terms of clock cycle delays. In order to understand how the latencies work, you must also understand how the memory reads and writes data.

DDR2 memory is a type of SDRAM. SDRAM stands for Synchronous Dynamic Random Access Memory. The memory is organized like a matrix or chart, with data arranged in rows and columns. The data is stored in blocks whose location are found by the coordinates of the specific rows and columns. Latencies come from the memory looking for the data in these series of rows and columns. The four most common latencies are:

• Column Address Strobe Latency (tCAS / CAS / tCL). This is the number of clock cycles needed to access a specific column of data.
• Row Address Strobe (tRCD, RAS). This is the number of clock cycles that it takes for the memory to actually start reading or writing from the time the coordinates of the data are defined.
• Row Precharge time (tRP) and is the number of clock cycles needed to end access to one row of memory and open access to the next row of memory.
• Active to Precharge Delay (tRAS) and is the number of clock cycles needed to access a specific row of data in the memory between the data request and the pre-charge command.

So what you have are 4 series of latencies. If you didn’t get much of the above paragraph, get this. The lower the latencies the better for system performance. However, lower latencies mean less stability at any given voltage. Common value of latencies are 3-3-3-X, 4-4-4-X, 5-5-5-X. The reason I put X in the last spot is because the latencies in this sport vary greatly, but are most commonly between 4 and 18 clock cycles.

Simply comparing memory latencies with considering the speed at which the memory is running those latencies is silly. This is because the overall latencies in nano-seconds is derived from dividing your total latencies in cycles by how many cycles your RAM can complete in one second. This gives you latencies per operation in seconds.

For example:

DDR2-800 does 800,000,000 cycles per second. Latencies of 4-4-4-12 add up to 24 cycles per operation of latency. Divide 24 cycles of latencies by 800,000,000 cycles and you get 30 nano-seconds worth of latencies per operation. However, DDR2-1000 with latencies of 5-5-5-15 also net you the same 30 nano-seconds of latencies per operation (30 / 1,000,000,000).

However, even though both settings have the same latencies. DDR2-1000 @ 5-5-5-15 is better than DDR2-800 @ 4-4-4-12, this is because DDR2-1000 has more data throughput when compared to DDR2-800.

Now, it is also a common myth that a system will be faster when it is "synced" (i.e. in a 1:1 ratio as apposed to a 5:4 ratio) with the processor. This is simply not true (or there is no substantial evidence to prove that it is true). Most people who will claim this and provide benchmarks are often missing a variable that would explain the difference in performance.

A few quick benchmarks proves this:

FSB = 200
Mutliplier = 9
CPU Speed = 1.8Ghz

@ 1:1 DDR2-400 Memory bandwidth = 3224MB/s
@ 2:3 DDR2-600 Memory bandwidth = 3774MB/s
@ 1:2 DDR2-800 Memory bandwidth = 4047MB/s

The majority of this guide was extracted from my overall Intel overclocking guide found here.

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Tyrker

Good read .

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Choggs396

Excellent Information. +1 Rep 4U.

Highly Recommended, people! You may learn something here!

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pauldovi

Bump

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stargate125645

How do you get 30 nanoseconds from the 24 listed there?

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gonX

tl;dr, but looks nice

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pauldovi

At DDR2-800 each cycle takes 1 / 800,000,000th of a second to run.

If you have 4-4-4-12, you have 24 cycles of latency.

24 / 800,000,000 = 30 nanoseconds.

I don't even know what that means...

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JohnRogers

Nice one Paul. An excellent read

rx7speed

just to help clarify as well on the latency vs mhz.
the latency number in itself means nothing without how many Mhz the ram is running at. 800mhz at 4-4-4-8 and 400mhz at 2-2-2-4 vs 1000 at 5-5-5-16 all have the same latency. as paul has said it is how many clock cycles it takes to do a given task. so if you double clock speed it does it twice as fast so with the above the higher numbers for latency still give the same reponce time.

either way +1 mr dovi

pauldovi

However, 800Mhz @ 4-4-4-8 is faster than 400Mhz @ 2-2-2-4 because it transfers data faster (even though it has the same latencies).

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