AMD Phenom II X4 955 HDZ955FBGIBOX 3.2 GHz/6 MB L3/125W Processor

True quad-core enabling cores communicate at die level. Direct Connect Architecture directly connects the processors, the memory controller and the I/O to the CPU. Enable simultaneous 32- and 64-bit, Integrated Memory Controller. Increases performance by reducing memory latency, Scales memory bandwidth and performance, HyperTransport Technology provides up to 16.0GB/s peak bandwidth/processor, reducing I/O bottlenecks, Up to 37GB/s processor-to-system bandwidth. Shared L3 cache (either 6MB or 4MB), 512K L2 cache/core, Shortening access times to highly accessed data. 128-bit FPU. BENEFIT: Larger data paths and quicker floating point calculations. One 16-bit link at up to 4000MT/s, Up to 8.0GB/s HyperTransport I/O bandwidth; Up to 16GB/s in HyperTransport Generation 3.0 mode, Up to 37GB/s processor-to-system bandwidth (HyperTransport bus + memory bus). BENEFIT: Quick access times to I/O. A high-bandwidth, low-latency integrated memory controller supports PC2-8500 (DDR2-1066); PC2-6400 (DDR2-800), PC2-5300 (DDR2-667), PC2-4200 (DDR2-533) or PC2-3200 (DDR2-400) SDRAM unbuffered DIMMs ¿ AM2+, Support for unregistered DIMMs up to PC2 8500(DDR2-1066MHz) and PC3 10600 (DDR3-1333MHz) ¿ AM3, Up to 17.1GB/s memory bandwidth for DDR2 and up to 21GB/s memory bandwidth for DDR3. Enhanced power management features automatically and instantaneously adjust performance states and features based on processor requirements enabling cooler and quieter platform designs. Power can be switched on or off within a single clock cycle, saving energy with no impact to performance. i.e, the memory controller can turn off the write logic when reading from memory, Works automatically without the need for drivers or BIOS enablement. Enables efficiency by dynamically activating or turning off parts of processor. Separate power planes for cores and memory controller, Improving efficiency by providing on demand memory performance while still allowing for decreased power consumption.