yes that is true, but doesn't matter. Its not a gimmick since power output is still high. That reviewer doesn't really understand how a SMPS power supply works, but ill clear it up for you. First you have a PWM, then you have what are called channels, which are phases. Each channel connects to a driver which then controls the MOSFETs that change 12v to whatever you set, then that power goes to the inductors(chokes) and capacitors(normal can type as well as high frequency ceramics) which are effectively storage, a low pass filter, and an output voltage "cleaner".
How everything works is what you need to know b/c otherwise you will not understand why we have phases. At any given moment only 1 pair of MOSFETs are to be on and converting power. Each phase, which in the end is a pair of MOSFETs and a driver(in the case of DrMOS the two MOSFETs and driver are all on one IC to reduce parasitics and increase efficiency while reducing the amount of PCB real estate needed) or one DrMOS per phase. Anyways the PWM outputs on each of its channels for our purposes outputs the switching frequency (which controls how many times per second the phase should be on) and duty cycle controlled offset (which controls what type of output). At the same time each PWM output is outputted at an offset so that each phase gets its signal after the phase before it. Effectively that is how the PWM controls the MOSFETs. The duty cycle or voltage out divided by voltage in gives a ratio that determines the output voltage, and the switching frequency determines how many times per second each phase will be on. The switching frequency is important, as you increase it you also increase heat and decrease efficiency, but when you decrease it you increase ripple and over and under shoot. So you need a balance, and that is determined by the characteristics of the DrMOS as well as the inductors and capacitor bank.
So in operation lets say the switching frequency is 250khz, so each phase is on by its own 250 thousand times per second, the output power is then stored int he inductor that it is attached too, and when the capacitors demand power the inductors discharge their stored power to the capacitors. The problem is transient response, if the switching frequency is too low then transient response will be low, and transient response is basically the overall speed that the power supply has, as in how fast you can change from a low power state to a higher power state as current and voltage are ALWAYS changing, and the speed of the change is very important. One HUGE thing that is always slowing down transient response is capacitor series resistance. Switching frequency is directly related to transient response as well. Ok so how does this apply?
Well they giuy talking about doubling has no idea about PWMs, as they are the MOST complex thing other than your CPU. Intersil is the manufacturer of the PWM on all Gigabyte boards, and no one else uses them, i think GB has some type of deal with them, plus they are very expensive. All GB boards use analog PWMs, meaning that the duty cycle control is done with hardware, with a amplifier and comparator with a voltage error, instead of firmware that compares to the error which would make it digital. Sot he analog PWMs are very quick, and have virtually no delays. This helps them use a lower switching frequency. On top of that intersil has its proprietary phase doubling scheme, which is stated in the white sheets to allow a 6 phase PWM control a 24 phase array, and a 4 phase PWm to control a 16 phase array. Each doubler has its own part number ISL6617, and the way they work is very secret, but after testing I have found that it does two things, it divides the switching frequency in half and then sets an offset to each phase as well as conserve the offset and OCP mechanisms. They basically allow a 4 phase PWM to quadrouple its phases effectively, without losing any characteristics of the original phase/channel, but it does divide the switching frequency by 2 each time, and your board will have 12 of the doublers. There is no such thing as a true 16 phase PWM on ANY motherboard, as they would be so expensive. The most i have seen is 10. Other companies double their phases almost the same, but usually blindly.
Now the typical switching frequency on lets say an asus board is 250khz, and then on those boards they HAVE to increase the switching frequency to OC higher than something like 5.3ghz, i remember an asus rep said that. On gigabyte boards its MUCH different. Since X58 every one of the GB boards uses these phase doublers and these same exact DrMOS. The reason being the technology of the PWM allows some crazy stuff. First off the PWM on the GB boards operates at 1mhz per phase 24/7, actually 1.05mhz i measured, and then each DrMOS gets 264khz effectivly 24/7. if you look at the efficiency chart and current output on the DrMOS youd see that at 300khz it can output 35A, and at 800khz it outputs something like 30A, and then at 1mhz its even less. This is becuase efficiency is decreased, no PWN and work 24./7 at high switching frequencies without great cooling, the EVGA classified was the one board i can think of that worked at 1mhz 24/7, and could go upto 1.33mhz, this feat has not been repeated. But many want higher switching frequency so that ripple and under/overshoot is decreased, but with the intersil APP and APA technologies there is no need for switching frequency above what has been stated. These techs are reserved only for this PWM and i have not sen them elsewhere, they are patented just like their doubler scheme. the reasont hese techs are possible is b/c the PWM uses interleaved channels.
Well interleaving the channels means that their individual ripple frequency and ripple amplitude can be multiplied together, this means lower ripple. This leads us to two Intersil technologies, Adaptive Pulse Positioning (APP) and Active Phase Alignment (APA).
The APA scheme can during VERY high current loads align all phases (usually they work one at a time so each channel switches 1/4 of the cycle after the channel before it) with this load scheme the PWM can turn all 4 channels on at ONE time when needed. so that ALL your phases are on at one time! but this is rarely used. The APP scheme banks on the interleaving and ripple effects which allows the use of lower bulk output capacitance which has an effect on dampening ripple. That is why on almost all GIGABYTE X58 and P67 boards you see so little bulk output capacitors, because of their high phase count.
Take a look count the number of capacitors on a lets say asus board and then a GB board of similar phase count.
This is the ISL 6617 datasheet: http://www.intersil.com/data/fn/fn7564.pdf
This is the data sheet for the PWM used: http://pdf1.alldatasheet.com/datashe...L/ISL6617.html
here is a quote from the ISl6617 datasheet:
"When the doubler operates in interleaving mode, the
PWM controller frequency should be set at two times the
desired phase frequency (FSW). Since the input PWM
pulse is divided into half to feed into each phase of the
doubler, the operational duty cycle of each phase should
be less than 50%. In synchronous mode, the PWM
controller should be operated at the same frequency as
the desired phase frequency. In this mode, the allowable
duty cycle is up to 100%. For cascaded interleaving, the
controller switching frequency needs to be set at four
times the phase frequency. During cascaded operation,
the maximum allowable duty cycle will be less than 25%."
Gb uses cascade mode on purpose instead of synchronized mode b/c there is no need for high SW, and that has been proven with the X58 boards, they hold WRs with their 264khz switching frequency compared to higher SF boards. Same goes for P67 the UD7 operates at the same SF as the UD4, the lower models actually use higher switching frequency.
That 16 phase VRM operates a true 16 phases. you can count phases by inductors, rather count them by the amount of DrMOS or pairs of MOSFETs, as some companies, the really less known, use more inductors and capacitors than there are MOSFETs!
Anyways the reduction in the capacitors helps reduce capacitor parasitics, but greatly increases transient response, so to make up for the loss in ripple control they increase the phase count which then reduces ripple through the interleaving, this approach allows for in the end much great power output, much greater efficiency, and the same ripple control as a board with much more bulk output capacitance.
Sorry its a lot to take in, in the end asus and gigabyte achieve the same goal through different means.
this might help you better understand VRM design, its my OC board review, it explains VRMs: http://www.overclockers.com/forums/s...d.php?t=676133Edited by Sin0822 - 6/13/11 at 6:28pm