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Bulldozer Live testing in China - Page 23

post #221 of 275
Quote:
Originally Posted by PureOC Jim View Post
You better hope they straighten this out or Intel chips will rise to premium pricing
Exactly! Exactly!!
    
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post #222 of 275
Quote:
Originally Posted by PureOC Jim View Post
He who laughs last laughs best.

You better hope they straighten this out or Intel chips will rise to premium pricing to cover Intels $300 million debacle smart arse.
Just because I'm not an AMD fanboy makes me an Intel Fanboy.

I'm neither. I support BD, I want BD. I need an affordable breadbox this winter.

I'm just irritated with AMD's approach at throwing more cores into a proc to make it better. I don't care about 8 cores. I want 4 that decimate the competition.

And I'm laughing because these preliminary figures for a supposedly "groundbreaking" proc are horrible!
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post #223 of 275
Quote:
Originally Posted by MediaRocker View Post
I'm just irritated with AMD's approach at throwing more cores into a proc to make it better. I don't care about 8 cores. I want 4 that decimate the competition.
Most uninformed consumers assume that more cores equals more speed. Unfortunately, catering to that ignorance as a strategy has made AMD a lot of money. The only drawback is that their brand is suffering because they simply do not have a credible consumer-level performance flagship anymore.

Hopefully these tests are either so preliminary that they are irrelevant or completely fake.
    
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post #224 of 275
its B0 .
When the BD arrives on the market only then we will see normal benchmarks , not from defect Eng sample that means nothing .
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post #225 of 275
Quote:
Originally Posted by Malcom28 View Post
its B0 .
When the BD arrives on the market only then we will see normal benchmarks , not from defect Eng sample that means nothing .
Its faster than my i5-2500k at stock (in 32bit cinebench). Which happens to be about a point slower than 64 bit.




What are you guys expecting?

10?

8?

lol. I think its fine, and working correctly. The problem isn't in its operation, the problem is in its clocks.

I'm guessing if that was 64 bit cine then he would have scored around 6.5, with stock clocks reaching 4.2Ghz he was slightly underclocked compared to retail chips. Which puts bulldozer a bit over 7 in 64 bit cinebench, imo.

Perhaps I'm wrong, but it looks fine to me. It will beat an i5-2500k and i7-2600k at stock in this benchmark. Maybe you're just excepting too much from a design that works slower per core so more cores could be added.

As I said in another thread, AMD isn't trying to beat Sandy at 5Ghz, they don't care about overclocking as neither company supports it. All they're trying to do is beat the i7-2600k at stock speeds in these types of tests, which is 3.5GHz with level 1 turbo for the i7-2600k.
Edited by BallaTheFeared - 6/11/11 at 4:10pm
    
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post #226 of 275
Balla;

The L2 & L3 cache is not working which will significantly affect performance. This is doubtful of being representative of a production chip watch the results from the AIDA memory benchmarks and you will notice that the L2 & L3 cache writes are not registering.
Edited by Kmon - 6/11/11 at 4:26pm
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post #227 of 275
Why do you think its not working? Because Aida isn't working correctly? It did the same thing with SB for weeks after SB went retail.

They'll release a "bulldozer" supported version after its released, just like they did for SB, just like CPU-Z/HWmonitor/RealTemp did as well.
    
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post #228 of 275
Quote:
Originally Posted by BallaTheFeared View Post
Why do you think its not working? Because Aida isn't working correctly? It did the same thing with SB for weeks after SB went retail.

They'll release a "bulldozer" supported version after its released, just like they did for SB, just like CPU-Z/HWmonitor/RealTemp did as well.
No, AIDA is working correctly but the cache is not as it is a simple. Also, if you read the original threat in the chiphell threat I think it post 789 they acknowledge the problem.

No the problem with the SB was that it uses a ring cache with caused problems for the software as it is a very different design for cpu. It is also why the SB has some good performance.

It is what it is accept the facts so the results of other benchmarks are non-representative.
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post #229 of 275
All post #789 said was this:

Quote:
Back next Pharaoh post

The CPU cache running AIDA64 tests, said it was found that L2 and L3 can not write
Are there any other programs that are also unable to write off the L2 and L3? Just because AIDA isn't I wouldn't rule it out as not working. I'd need a bit more proof.
    
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post #230 of 275
Balla

Regarding the sandy brige ring cache from Anandtech interview

"The Cache

As a consequence of increased integration, Intel had to address the ways bits and pieces of its processor were accessing the last-level cache (in Sandy Bridge, it’s the L3).

The ring bus, as it appears in Intel's Xeon 7500-series
Earlier this year, I had the chance to talk to Sailesh Kottapalli, a senior principle engineer at Intel, who explained that he’d seen sustained bandwidth close to 300 GB/s from the Xeon 7500-series’ LLC, enabled by the ring bus. Additionally, Intel confirmed at IDF that every one of its products currently in development employs the ring bus. Think we’re going to see a continued emphasis on adding cores and other platform components directly to the CPU die? I’d say that’s a fair assumption.

Of course, Intel wasn’t worried about higher core count on the mainstream desktop version of Sandy Bridge. Rather, it was the on-die graphics engine that compelled a similar shift to the ring bus architecture, which now connects the graphics, up to four processing cores, and the system agent (formerly referred to as uncore) with a stop at each domain. Latency is variable, since each component takes the shortest path on the bus; overall, though it’s always going to be lower than a Westmere-based processor.

At the end of the day, the ring bus’ most significant contribution is going to be the performance it facilitates in graphics workloads. "

Balla, accept facts that a degrade or non working cache is going to impact performance. You do know what the L2 & L3 cache does? Please provide an explaination how it is not going to affect performance.

This should be fun.
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