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Bulldozer Live testing in China - Page 24

post #231 of 275
You still haven't shown it wasn't working in anything except write, nor any in other program but Aida.

The performance impact of Cache could be decent or negligible, just like the difference between 6mb on the i5 8mb on the i7 means almost nothing.

There are other programs to test cache, have him run Sandra, since hes clearly taking requests.

I don't believe even if L2 and L3 weren't working properly you'd see a giant leap in performance for them working correctly. Again, what are you guys expecting from bulldozer? Its already as fast as the i7-2600k.
    
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post #232 of 275
Balla;

If you answered the questions you will know a degrade or non-functional cache is going to impact performance? All programs are affected. Do you understand computer architecture?
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post #233 of 275
Yes I do, but you still have not shown that it is actually defective.
    
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post #234 of 275
Balla

Answer the questions asked?

Another burp from anandtech that evalautes cache size.

"The L2 cache has been known to be very efficient, especially since it is shared by both processor cores. Hence, it can level the impact of different RAM speeds and prevent Front Side Bus bottlenecks. And it does so very well, as we could see how the test processor's performance with only one megabyte second level cache fell clearly behind."

It doesn't matter, you refuse to understand and recognize facts. Either you clearly do not understand computer architecture or just want to convey disinformation.

Enough said.
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post #235 of 275
No, all I'm saying is that you have no proof the L2 and L3 write are broken.

Do you have the actual numbers from Bulldozer to state that without question his is broken?

You do understand he ran 32 bit cinebench, with a 600Mhz overclock on the i5-2500k vs, a underclocked bulldozer chip right?

Does that compute?

Could you run your 1090T at stock 3.2GHz in 32 bit cine and post the results. Can you do that?
    
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post #236 of 275
You really dont accept facts

Look at the video that he posted when he runs the AIDA memory benchmark. As you can see it is not recording anything for L2 & L3 writes.


From the AMD Bulldozer optimization guide: http://support.amd.com/us/Processor_TechDocs/47414.pdf

“2.5.3 L2 Cache
The AMD Family 15h processor has one shared L2 cache per compute unit. This full-speed on-die L2 cache is mostly inclusive relative to the L1 cache. The L2 is a write-through cache. Every time a store is performed in a core, that address is written into both the L1 data cache of the core the store belongs to and the L2 cache (which is shared between the two cores). The L2 cache has an 18-20 cycle load to use latency. Size and associativity of the AMD Family 15h processor L2 cache is implementation dependent. See the appropriate BIOS and Kernel Developer’s Guide for details.

2.5.4 L3 Cache
The AMD Family 15h processor supports a maximum of 8MB of L3 cache per die, distributed among four L3 sub-caches which can each be up to 2MB in size. The L3 cache is considered a non-inclusive victim cache architecture optimized for multi-core AMD processors. Only L2 evictions cause allocations into the L3 cache. Requests that hit in the L3 cache can either leave the data in the L3 cache—if it is likely the data is being accessed by multiple cores—or remove the data from the L3 cache (and place it solely in the L1 cache, creating space for other L2 victim/copy-backs), if it is likely the data is only being accessed by a single core. Furthermore, the L3 cache of the AMD Family 15h processor also features a number of micro-architectural improvements that enable higher bandwidth. “

As a result the non functioning L2 & L3 write cache is seriously going to impact performance.

From the AMD Bulldozer optimization guide:

"2.15.1 Hypertranport Assist
HyperTransport assist also increases the total coherent fabric bandwidth capability within the system by removing much probe and response traffic from the coherent HyperTransport links. It also streamlines probe and response handling throughout the L1/L2/L3 caches and elsewhere in the microarchitecture, which can lead to additional bandwidth improvements in systems with multiple processing nodes. HyperTransport assist is enabled by partitioning the L3 cache physical storage into a section used as traditional (CPU-side) L3 cache, and a separate physical section for directory storage which is inaccessible to the CPUs. In effect, from the perspective of CPUs, systems with HyperTransport assist enabled have a smaller L3 cache. Typically, 1–2MB of L3 cache is reserved for use by HyperTransport assist technology. Thus, some amount of L3 capacity is traded for reduced latency on cache refills. While the benefit of this tradeoff can be workload-dependant, it is almost universally a win on larger (4+ node) systems. If a platform runs a specific workload, it may be worth evaluating performance with and without HyperTransport assist.”

Stop with the disinformation. Provide a written explanation how the non cache ability to write is NOT going to impact performance expecially since the above is taken from the Bulldozer optimization guide .

DO YOU UNDERSTAND WHAT THE IMPLICATION OF A WRITEBACK does to performance and the capping of bandwidth.
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post #237 of 275
Quote:
Originally Posted by Kmon View Post

Balla, accept facts that a degrade or non working cache is going to impact performance. You do know what the L2 & L3 cache does? Please provide an explaination how it is not going to affect performance.

This should be fun.
Seems like he wants BD to be slower than SB?
AMD's action of disabling L2&L3 cache as well as the turbo being broken,and capping the clock speed is most likely on purpose so actual benchmarks are not leaked before release.
The B0 and B1 steppings are for testing only,and do not correlate with the improved revision AMD is working. AMD said no benchmarks before release date.
Why go showing off real pre-release benchmarks when your competitior can easily roll out their next gen tech early?
Llano will hit them first,then BD will come as a surprise and hit them again.
Edited by Heavy MG - 6/11/11 at 6:05pm
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post #238 of 275
In its current state it is faster than SB, at least the i5-2500k. I haven't seen any i7-2600k stock results in 32 bit however I would assume they would be pretty even there.


All I'm saying is that the bulldozer chip is underclock from what the factory clocks will be. And its meant to compete against stock SB chips, not overclocked chips.


I'm not going to throw my hands in the air and say L2 and L3 are disabled because it gives readings for read and copy, just not write. It could be as simple as the program not having the right information to read it back. Its as simple as that. Just because AIDA isn't giving a result on write doesn't mean its disabled.
Edited by BallaTheFeared - 6/11/11 at 6:07pm
    
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post #239 of 275
Quote:
Originally Posted by BallaTheFeared View Post
In its current state it is faster than SB, at least the i5-2500k. I haven't seen any i7-2600k stock results in 32 bit however I would assume they would be pretty even there.


All I'm saying is that the bulldozer chip is underclock from what the factory clocks will be. And its meant to compete against stock SB chips, not overclocked chips.
Why wouldn't a overclocked FX compete with overclocked chips?
AMD knows what overclocking is,they even say "FX is unlocked out of the box!" And If I remember correctly AMD also stated FX can be "overclocked for maximum performance".
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post #240 of 275
They still don't support it.

We havn't seen what an overclocked bulldozer chip can do because the people who have them are running them around 4GHz, which is actually BELOW stock for the flagship chip.

Why can't Phenom II compete with 1366? I dunno, its just the way it is sometimes. You guys seem to be expecting the second coming. Its not slow by any means, its not Intel per core fast, but that was never their intention.
    
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