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Bulldozer Live testing in China - Page 28

post #271 of 275
The 7.2 is not a Cincebench score. We are talking about the efficient of a bulldozer core module ( 4 modules is worth about 7.2 bulldozer cores). I guess you didn't read the whole thread.
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post #272 of 275
Quote:
Originally Posted by Xristo View Post
i get 7.2 points with my i7 in cinebench , not very impressive bulldozer .
64 bit I'm presuming?

I get 8.4, so its going to take over 16 points from the x8 for the x4 to matter to me.
    
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post #273 of 275
Quote:
Originally Posted by Xristo View Post
i get 7.2 points with my i7 in cinebench , not very impressive bulldozer .
As of now,the only cinebench scores are from a ES BD being ran in 32bit cinebench,which provides different results than 64 bit cinebench.
Quote:
Originally Posted by BallaTheFeared View Post
Wow, you listened to what I had to say Heavy?

<3
Lol,I just kind of reiterated what you said. You did give some good insight on why the result looked fake or too low.
Why does 32 bit ciebench give different scores than the 64 bit version?

I ran a cinebench 32 bit on my old Centrino laptop for the lulz.....0.86 ftw.
Edited by Heavy MG - 6/12/11 at 5:47pm
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post #274 of 275
Wow, you listened to what I had to say Heavy?

<3
    
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post #275 of 275
Since Balla is not going to answer the questions surround cache. This information was gather from various sources.

Interlagos has a 16-way associative design. What does this mean??

"The load-to-use latency for Bulldozer is going to be surprisingly high probably around 18-20 cycles--and in comparison, the L2 caches for Nehalem and Istanbul are roughly around 10 cycle latency. That also means The L2 cache can have as many as 23 outstanding misses concurrently. Since the L1D is both write-through and mostly included in the L2, evicting a cache line from the L1D is silent and requires no further actions. This is beneficial since evictions are typically caused by a filling a cache line, in response to a cache miss and closely tied to the critical path for a miss."

It appears that the L1D is mostly included in the L2. As a result, there are going to be certain situations where lines are going to be residing in the L1D without being present in the L2. This result in the L1D may need to be snooped when another core misses in the L3 cache. Snooping is not wanted to occur since that puts a large amount of traffic in the BD system. Bulldozer was designed to eliminate snoop traffic to the L1D caches and instead have the L2 cache for each module handle all the coherency snoops for that module. This is a Design improvement !!

There is a disadvantage of a write-through policy though and that is the L1D caches do not insulate the L2 cache from the store traffic in the cache hierarchy. Now, L2 cache must have higher bandwidth to accommodate all the store traffic from two cores, and any associated snoop traffic and responses. Hopefully, BD architecture has solved this problem by including a write coalescing cache (WCC), which is considered part of the L2.

Intel has historically focused upon Prefetching where AMD has always lagged behind. It has already been stated that Prefetching for Bulldozer will be non-strided data prefetcher's. Also, bulldozer is going to have independent prefetchers at both the L1 and L2 levels supporting a larger numbers of strides and large stride sizes

Architecture overview of Bulldozer is attached
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