* Ditch the VLIW instruction format and move to SIMD wide-vector execution
* L1 and L2 read / write caching
* Out of order resource allocation
* ECC data protection on SRAMs and global memory
* Parallel primitive
A few highlights from the talk: Multiple primitive pipelines for setup, etc.
Real caching in L1, L2, separate color / z caches for graphics and atomics
Out of order resource allocation
ECC on srams and drams
So, basically what I got from that is that these new cards will be able to multitask better, have faster access to information, and that the processors will also be able to handle more information vs the current implementation of instruction sets.
All of that sounds really nice. Q4 2011 is a really long time though, I was thinking that maybe they would be out in a month or so, I even sold my cards in my desktop and went laptop full time. Maybe too soon perhaps.
Probably a mid December release, like the 6000 series.