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Need help with overclocking basics

post #1 of 2
Thread Starter 
Hi members,

I need some help to understand the basics of overclocking. I dont really know where to start, i'll try to be has clear as possible.
On some post David asks:
Quote:
Should the DDR2 memory DRAM Frequency be as close to the Bus Speed of the CPU as possible?
David specs:
Quote:
DRAM Frequency - 301.1 MHz
FSB : RAM - 2:3
CL, tRCD, tRP - all 4 clocks
Cycle Time - 12 clocks
Core Speed 3010.8 MHz
Multiplier - x15.0
Bus Speed - 200.7 MHz
FSB - 802.9
Then paul explain that we should consider the real transfer rate in mb/s of both the memory and the processor bandwidth to match.

Paul calculs:
Quote:
if you had dual channel memory at PC2-4800 (which is DDR2-600 rate),
the bandwidth might look like 2*4800 = 9600MB/sec
The processor is 8 * FSB800 = 6400MB/sec.
The first calcul is 4800 * 2 because its in dual channel thats ok.. But on the processor one (8 * FSB800) where does the 8 come from?

I also have some other question about this after someone help me get this clear.
post #2 of 2
Thread Starter 
With google, i have some progress:

Quote:
8 counts as the amount of "bits" per data cycle.
Before i can understand this, there comes another question: How can i know how many transfers per Clock Cycle my cpu can do?

Quote:
Number of cores 2 (max 2)
Number of threads 2 (max 2)
Name AMD Athlon 64 X2 5200+
Codename Windsor
Specification AMD Athlon(tm) 64 X2 Dual Core Processor 5200+
Package Socket AM2 (940)
CPUID F.3.2
Extended CPUID F.43
Brand ID 4
Core Stepping JH-F2
Technology 90 nm
Core Speed 2612.2 MHz
Multiplier x FSB 13.0 x 200.9 MHz
HT Link speed 1004.7 MHz
Stock frequency 2600 MHz
Instructions sets MMX (+), 3DNow! (+), SSE, SSE2, SSE3, x86-64, AMD-V
L1 Data cache 2 x 64 KBytes, 2-way set associative, 64-byte line size
L1 Instruction cache 2 x 64 KBytes, 2-way set associative, 64-byte line size
L2 cache 2 x 1024 KBytes, 16-way set associative, 64-byte line size
FID/VID Control yes
Max FID 13.0x
Max VID 1.350 V

Edited by iOL - 8/20/11 at 1:58pm
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