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[Intel] Intel Discloses New Architecture Features of Next Generation Itanium... - Page 4

post #31 of 34
Quote:
Originally Posted by hajile View Post
What follows are small excerpts from a fascinating, but lengthy article. The rest is certainly worth the read.
tl;dr so what is the summary?
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post #32 of 34
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Originally Posted by Ubernoobie View Post
tl;dr so what is the summary?
that was a summary (albeit a somewhat unsummary one).

Itanium has adopted many of the best features of Xeon and will have huge (> 50% 280%) increases in performance while also increasing reliability, decreasing power consumption, and decreasing die size by 30%.
Edited by hajile - 8/23/11 at 11:30am
post #33 of 34
Quote:
Originally Posted by hajile View Post
if reliability is approximately equal and performance is much higher, there is still a market. Also worth noting is that if the reliability of a 700mm^2 chip (current Itanium) is equal to a 260mm^2 chip (current Nehlem), when the size of the Itanium drops to 540mm^2 (poulson) the reliability will increase due to smaller die size and thus (likely) provide more reliability.
However, reliabilty isn't just about die size and transistor count. Validation and binning play a bigger part in reliability.

A 1000mm^2 chip can be more reliable than a 50mm^2 part.
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post #34 of 34
Quote:
Originally Posted by DuckieHo View Post
However, reliabilty isn't just about die size and transistor count. Validation and binning play a bigger part in reliability.

A 1000mm^2 chip can be more reliable than a 50mm^2 part.
The percentage of valid chips is primarily a combination of chip design, fabrication technique, and die size. If two chip designs are equally optimized for a particular fabrication technique (it is a a reasonable assumption that Intel knows how to optimize its own chips for its own fab), then the largest factor in reliability is the chip's die size.

In the world of special HPC/server chips, either chips are valid or they are not. This is even more true for Itanium where chips that do not pass the quality control are eliminated due to a lack of secondary markets (companies do not buy Itanium with low cost or low power in mind, they are either software dependent, or need the raw power). Only a few chips are binned in fact there are only four different Itanium binnings at .10 Ghz apart for a small spread of only .40 Ghz(intel) as compared to a 1.86 Ghz spread for the 5600 series xeon(intel).

Intel can increase performance a lot while keeping current reliability or increase performance a little less than the maximum possible and improve reliability.
Quote:
Given the scope of the changes, performance per core could improve by 25-40%, through a combination of higher frequency and IPC. On top of that, the core count has doubled, so the net gain could be as high as 2.8X. For workloads that are memory and I/O bandwidth limited, the gains will be substantially smaller, but still significant.

Poulson's microarchitecture (Figure 8) should increase instructions per cycle by 10-15%. Dynamic scheduling will boost IPC, although to a lesser extent than full blown out-of-order execution; and removing the NOPs is also fairly helpful. The 12-wide back-end can swiftly clear all the stalled instructions when a cache miss is resolved; helping average IPC, even if the core is only 6-wide due to fetch and decode constraints. Poulson's better multithreading and replicated DTLBs will raise utilization of the execution pipelines and data caches significantly and help hide low latency events (e.g. L1 or L2 cache misses). The only loss of IPC in the core should come from scaling back to 2 memory pipelines - but for most software, this is a small factor. (realworldtech)
All this said, I think EPIC needs to disappear leaving the world with x86, SPARC, and POWER for HPC.

edit: Intel also increased Itanium reliability via greatly improved error checking and correction (something not likely to make its way into xeon due to die constraints and need to reuse cores for laptop and desktop designs).

Quote:
Itanium is intended for mission critical and high availability servers and reliability has always been an integral part of the design. Smaller process technologies are more susceptible to soft errors – so reliability features in a chip must improve merely to keep errors from rising. Intel claims that Poulson reduces the number of errors, despite doubling the cores. The L3 cache ECC is more robust – with a double error correct and triple error detect (DECTED) algorithm rather than conventional SECDED – in part so that it can operate at 0.9-1.1V to save considerable power. Inline ECC has been added to the L2 caches and tags, as well as the directory caches in the home agents. The L1 caches are implemented using more reliable 8T storage cells and parity. Almost all register files also have parity protection; the integer and floating point register files even have ECC. In addition, many latches (temporary storage for data as it flows through the pipeline) have been radiation hardened. (realworldtech)

Edited by hajile - 8/23/11 at 11:35am
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