Originally Posted by bane-o
may be a little off topic, but can someone point me in the direction of some reading material about this "CPU hard wall" I've never heard of it and a quick google search didn't really give any useful results. Is it anything like a FSB hole?
there are theories on why it exists, when i was at IDF, i attended Intel's "OC class" there were interesting questions asked by a few people.
but after the class i asked about CPU PLL Overvoltage from one of the engineers who works on overclocking, yea they really have OC engineers, that is probably why CPU PLL overvoltage exists, and why SB OCes so freely.
Anyways CPU PLL overvoltage is one of the BIOS settings, that is usually hidden, and disabled. When disabled it "clips" an internally derived voltage that powers the CPU PLL. So the motherboard uses a linear regulator, or just a simple step down converter to push 1.8v stock into the CPU(and the user can change this voltage), it along with the CPU Voltage, iGP voltage, and system agent and qpi/vtt voltage are the major voltages the board provides the CPU. From there the CPU has a power control unit, the PCU, this controls power to different segments using the voltage supplied to the CPU as well as uses TDp and TDC to limit overclocking(but board makers get around this).
Now the CPU have a few PLL(phase lock loop) they produce frequencies like a clock generator, now internally that 1.8v might only have 60mv fed to the PLL that controls the clocks for the CPu frequencies bins, that 1.8v is clipped down to 60mv for that specific PLL, and then that allows that 1.8v to then also be used for another voltage as well totally separate from the PLL which CPU PLL overvoltage affects. Well with the CPU PLL over-voltage enabled it could potentially "clip" less of that voltage and produce 70mv or 65mv extra to the CPU's internal PLL. That is why no one found that when CPu PLL Over-voltage is enabled, and CPu PLL voltage is increased to the CPU, that it doesn't help OC, instead in many cases lowering CPU PLL helps. Maybe that voltage is used for a bunch of different PLLs, and the CPU PLL voltage the motherboard provides and you can control has a great impact over the amount of cold the CPU can take, and it has for many generations of intel CPUs. Thus from that 1.8v being used for different internally derived voltages.
The Engineer said that they found that with that setting enabled the SB CPUs had 4-5X multipliers higher than with it disabled, and that they are constantly looking for more settings like that, that might be helpful to OC. That is why when the board makers found out about CPU PLL Overvoltage right before launch, they were all about to get it into their BIOSes overnight, literally. That is because it was a setting already there, just hidden b/c it was thought there was no use. Its also no coincidence that Intel boards had it first. The Engineer also said that over time that setting set to enable can have an impact like increasing the CPU voltage.
So anyways they have artificially limited the max CPU multipliers, as the potential of the CPU is huge, you see how it OCes on air, BD OCes about the same on air, and it just set a WR. But intel uses a different silicon than AMD, its manufacturing is different, that is why AMD doesn't really have too many cold issues, but intel has many. Sandy Bridge is not alone. you can run Sb at -150C, but in most cases the CPu wont scale lower than -20, and that hurts it potential.
Then you have CPUs, that no matter what you do cannot hit over 5.5ghz or eve 5.2ghz, no matter the temp, no matter the voltage. In that case there is an artificial wall, either by the way they bin the Sb CPU, or by some factory settings/manufacturing tolerances. No one has hit the max MHZ that is possible with 59x and max BLCk of even 104mhz(most ppl can get more BLCk, like even up to 110 in many cases), no one has hit over 6050mhz. So maybe there are setting like CPU PLL Overvoltage that are still set to disable, and on some processors the variation of the clipping varies due to tolerances.
but then that theory can be debunked by the fact that even if the CPU is in the same batch, they OC totally differently, its totally random. Intel will never come out and say hey will set the max multiplier/frequency for each CPU randomly, and we are doing it to limit its OC potential, they would never do such a thing. Why? it would kill a huge market, so many companies build boards for OC, make memory for OC, make coolers for OC, make power supplies for OC, put up OC events, marketing, there is such a huge market, for the two largest motherboard makers to release boards specially designed for overclocking, and for those with much less resources to follow.
There were two ways one could tell the OC potential of a CPU, well really 3 ways:
#1 the VID, the stock voltage that is set at the factory, the lower the better
#2 the batch, once you know one CPU OCes that high, the others int eh same batch will do the same, that is why you see people list batch numbers when selling a i7 900 series CPU or similar gen, and you don't see it anymore really with SB.
#3 the TDP, now CPUs with lower TDP will OC higher with normal cooler, water or air. BUT ES CPUs have NO SET TDP, and that is why ES CPUs of previous Gens OC SO MUCH higher than retails in many cases. TDp is a variant of the leakage of the transistors in many cases, but other variables as well. Usually on retail CPus it is locked, at like 95W for example. The leakier a transistor the higher its potential frequency, that is how NVIDIA decreased the TDp from the GTX 400 to GTX 500 series, the rearranged the higher and low leakage transistors, and then added a third one with mid leakage. On an unlocked ES CPU, the TDp could be something like 300W on like a i7 990x, of course that is not always what makes it a great OCer, but ti is why most ES OC higher than retail.
Now Sandy Bridge kills #1 and #2, they just don't apply, and #3 really doesn't either, ES SB CPUs are bull****, and junk at most. maybe the whole issue is that Intel is trying to do away with ES CPUs winning WRs, that is probably the case with #3 and CPU PLL Overvoltage, because even after they found the settings, they said no ES CPU D1 stepping, which are the majority of ES LGA1155 chips can use the setting, you can't even boot into windows with it set on with an ES D1 stepper.
Intel is doing this more or less, or they radically changed something in the architecture that cannot operate higher than 6ghz, which I don't get. Most say its because of the 100mhz bus on everything, but with SBe those busses are now separated again, and SBe isn't OCing as high as many had hoped.
ivy bridge will be a bit different, they raised the max multi to 63x, so we should see boards with 65X potentially. Bottom line, you cannot predict how well any SB CPU will oC only 3 out of thousands have hit 6ghz, yet SB still owns most platforms in many benchmarks.