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AMD FX (Bulldozer) Owners Club! - Page 335

post #3341 of 8112
Upgraded to a FX-8120 from FX-6100, time to see the real power of these bulldozer chips!
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post #3342 of 8112
Quote:
Originally Posted by L0GIC View Post

Upgraded to a FX-8120 from FX-6100, time to see the real power of these bulldozer chips!

You had better HANG ON now... thumb.gif
post #3343 of 8112
ok ive figured out the first line of code on the processor lid
now can someone tell me or link me a site to tell me what the second and third lines are or that can break it down
i know the stepping and manufacture date are somewhere in the second line just not sure where
post #3344 of 8112
Quote:
Originally Posted by vedaire View Post

ok ive figured out the first line of code on the processor lid
now can someone tell me or link me a site to tell me what the second and third lines are or that can break it down
i know the stepping and manufacture date are somewhere in the second line just not sure where

http://www.techspot.com/vb/topic173211.html
Quote:
The CPU and the box should both tally : FD8120FRW8KGU. The GU part refers to B2 stepping.

The rest if you're interested:
F = FX series, D = Desktop, 8120 = SKU, FR = 125w TDP, W = AM3+ socket, 8 = 8 core, K= 8MB L3 cache.

I am not sure about manufacture date though
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post #3345 of 8112
Quote:
Originally Posted by Seronx View Post

Integer Cores do not compete with each other
The Cache has buffers(L1i has a 256 Byte buffer per core and L2 has a 4 Kilobyte Buffer for each core)
Floating Point has an OoO scheduler which prevents decreases in performance
Sustained IPC is always 4 with each core

http://semiaccurate.com/2011/10/17/bulldozer-doesnt-have-just-a-single-problem/
Quote:
The front end is also a big problem. Bulldozer’s front end can decode four instructions per clock vs three in Stars, and Intel’s Sandy Bridge also can do four per clock. This would be an advancement if that front end serviced one integer core, but it doesn’t, it services two. That front end can switch on a per-clock basis, feeding one core or the other, but not both in one clock.

Integer cores will compete for resources, it can NOT decode 4 instructions per Int core. Its 4 instructions per clock for a module.

Although it is also noted in that article...
Quote:
The integer cores have two ports per core vs three on the older architectures, so theoretically this 4 instruction issue per two clocks isn’t a big problem, but since IPC does indeed go down in the real world vs Stars, it doesn’t seem to work out well in practice. That said, keeping a two pipe core close to a three pipe core in single threaded integer performance is a pretty amazing feat, but the competition has more decode, more threads, and overall better performance. Peeling out the actual effect on performance is almost impossible, but there is unquestionably one. Slice a few more cuts here.

Edited by KarathKasun - 1/26/12 at 5:36pm
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post #3346 of 8112
Quote:
Originally Posted by KarathKasun View Post

Integer cores will compete for resources, it can NOT decode 4 instructions per Int core. Its 4 instructions per clock for a module.
Although it is also noted in that article...

Nope, the instruction fetch is decoupled from the instruction decode

The decoder can decode 8 macro-op instructions per clock

8 macro-op instructions => 16 micro-op instructions
Quote:
A single micro-op
specifies only one of the
following primitive
operations:
• Integer or floating-point
• Load
• Store
Quote:
A single macro-op may
specify—at most—one
integer or floating-point
operation and one of the
following operations:
• Load
• Store
• Load and store to the
same address
Quote:
16-entry (per-thread) Instruction
Byte Buffer (IBB).

The IBB buffers 16 Macro-ops per core and 8 Macro-ops can be decoded per cycle and 8 Macro-ops can retired per cycle
(4 per core)

Charlie isn't a good architect
Edited by Seronx - 1/26/12 at 6:40pm
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post #3347 of 8112
Hey rather new to overclocking

successfully overclocked FX8150 to 4.407.2ghz using a cool master hyper 612, and antec 6 thermal paste. My question is at max load I am hitting 62 c voltages are ok as well. Wondering if this temp is acceptable. Still doing long term test with prime95 overnight wprime test passed, linX passed.

Any tips would be helpful
post #3348 of 8112
Quote:
Originally Posted by willup View Post

Hey rather new to overclocking
successfully overclocked FX8150 to 4.407.2ghz using a cool master hyper 612, and antec 6 thermal paste. My question is at max load I am hitting 62 c voltages are ok as well. Wondering if this temp is acceptable. Still doing long term test with prime95 overnight wprime test passed, linX passed.
Any tips would be helpful

Where did you find your version of linX? I haven't found a copy yet that works with my FX6100.
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post #3349 of 8112
Quote:
Originally Posted by willup View Post

Hey rather new to overclocking
successfully overclocked FX8150 to 4.407.2ghz using a cool master hyper 612, and antec 6 thermal paste. My question is at max load I am hitting 62 c voltages are ok as well. Wondering if this temp is acceptable. Still doing long term test with prime95 overnight wprime test passed, linX passed.
Any tips would be helpful

Max recommended temp for 8 core FX processors is 61C for core temp...
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post #3350 of 8112
Quote:
Originally Posted by mikezachlowe2004 View Post

Max recommended temp for 8 core FX processors is 61C for core temp...

It can handle 97+ degrees centigrade just fine rolleyes.gif

32nm-SHP Tj Max is 115 degrees centigrade
Edited by Seronx - 1/26/12 at 8:31pm
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