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VHDL - Nested If Statements

post #1 of 2
Thread Starter 
I have the following excerpt from a working VHDL model:
Code:
...

Port ( NUM : in  STD_LOGIC_VECTOR (3 downto 0);
           F : out  STD_LOGIC_VECTOR (7 downto 0);
           L : out  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0));

...

BCD_7DECODER: process (NUM,B)

begin

if (NUM="0000") then F <= "00000011";
elsif (NUM="0001") then F <= "10011111";
elsif (NUM="0010") then F <= "00100101";
elsif (NUM="0011") then F <= "00001101";
elsif (NUM="0100") then F <= "10011001";
elsif (NUM="0101") then F <= "01001001";
elsif (NUM="0110") then F <= "01000001";
elsif (NUM="0111") then F <= "00011111";
elsif (NUM="1000") then F <= "00000001";
elsif (NUM="1001") then F <= "00001001";
elsif (NUM="1010" AND B(3)='1') then F <= "00010001";
elsif (NUM="1011" AND B(3)='1') then F <= "11000001";
elsif (NUM="1100" AND B(3)='1') then F <= "01100011";
elsif (NUM="1101" AND B(3)='1') then F <= "10000101";
elsif (NUM="1110" AND B(3)='1') then F <= "01100001";
elsif (NUM="1111" AND B(3)='1') then F <= "01110001";
else  F <= "11111111";
end if;

end process;

...


For last few elsif statements that have B(3)='1', I want to embed another if statement so that it checks to see if B(3) is 1 before ever checking the value of NUM.
Code:
...

if (NUM="0000") then F <= "00000011";
elsif (NUM="0001") then F <= "10011111";
...
...
elsif (NUM="1001") then F <= "00001001";
if (B(3) = '1') then
if (NUM="1010" ) then F <= "00010001";
elsif (NUM="1011") then F <= "11000001";
elsif (NUM="1100") then F <= "01100011";
elsif (NUM="1101") then F <= "10000101";
elsif (NUM="1110") then F <= "01100001";
elsif (NUM="1111") then F <= "01110001";
end if;
end if;
                else  F <= "11111111"
end if;

...

However, that doesn't work properly when I try to nest an if statement. The model will synthesize and generate a bit file for the FPGA; there are no warnings or errors. However, nothing happens for the parts where the nested if statement is. What am I doing wrong?
Edited by stn0092 - 10/12/11 at 6:59pm
LancelotX79
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LancelotX79
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post #2 of 2
Look closely at you VHDL.
Code:
elsif (NUM="1001") then F <= "00001001";
if (B(3) = '1') then
                      if (NUM="1010" ) then F <= "00010001";
In this spot you are potentially assigning 2 values to F, which on too many FPGAs, the second assignment could be ignored (or "optimized out"). Some of the time they do not throw warnings or errors when doing this, it may only be a info message.

You want to do it slightly different to make it clearer to the synthesizer what you are trying to do:
Code:
if (NUM="0000") then F <= "00000011";
elsif (NUM="0001") then F <= "10011111";
..snip..
elsif (NUM="1001") then F <= "00001001";
else 
      if (B(3) = '1') then
 if (NUM="1010" ) then F <= "00010001";
 elsif (NUM="1011") then F <= "11000001";
 elsif (NUM="1100") then F <= "01100011";
 elsif (NUM="1101") then F <= "10000101";
 elsif (NUM="1110") then F <= "01100001";
 elsif (NUM="1111") then F <= "01110001";
     else
         F <= "11111111";
     end if;
end if;
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