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[Xbitlabs] Ex-AMD Engineer Explains Bulldozer Fiasco: Lack of Fine Tuning - Page 4

post #31 of 51
Quote:
Originally Posted by Foxdie;15308916 
now when you say processes and software what do you mean by that? so then how do we attribute the lower performance if it wasn't architecture nor design process?

you should maybe make a thread explaining why bd wasn't as good as it is..
I'll be discussing it in detail tomorrow on the Overclock.net Podcast

What I mean by Software, is that most Software is optimized for the SSE2 instruction set, and that's it. Sometimes it's optimized to use SSE3, but right now; both Intel & AMD have the SSE4.2 Architecture.
Like wise, they're working on the SSE5 instruction set which AMD already implements parts of on the current generation bulldozer chips.

As for process, the 32nm Manufacturing Process from Global Foundries has had nothing but problems for AMD which initially gave them poor yields. (Which they fixed, and is why you see only the FX-6xxx & FX-8xxx chips right now.) Though, just because they got past poor yields didn't mean they made it past other parts, they still had issues with leakage and other various atributes of the process which is the main reason why Bulldozer runs "hot" and uses so much power.
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post #32 of 51
Intel uses a lot of automated design tools too...
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post #33 of 51
Quote:
Originally Posted by kartcrg84;15309025 
I think that it is also important to keep in mind that had AMD hand crafted more of there processors, Bulldozer would have been delayed even more, since hand crafting generally takes longer. I think that if AMD had taken any longer to release Bulldozer, they would be in even worse shape. As it stands, at least they have something on the market that the average stupid consumer will buy.
See, the article gives you that idea, but it's wrong.

Bulldozer Delays are almost entirely on Global Foundries 32nm process being bugged.

Like wise, Intel uses Automated design on their Sandy Bridge chips. They've been doing Automated Design on most chips since the Conroe days, 6 years ago.
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post #34 of 51
Quote:
Originally Posted by Tator Tot;15309049 
I'll be discussing it in detail tomorrow on the Overclock.net Podcast

What I mean by Software, is that most Software is optimized for the SSE2 instruction set, and that's it. Sometimes it's optimized to use SSE3, but right now; both Intel & AMD have the SSE4.2 Architecture.
Like wise, they're working on the SSE5 instruction set which AMD already implements parts of on the current generation bulldozer chips.

As for process, the 32nm Manufacturing Process from Global Foundries has had nothing but problems for AMD which initially gave them poor yields. (Which they fixed, and is why you see only the FX-6xxx & FX-8xxx chips right now.) Though, just because they got past poor yields didn't mean they made it past other parts, they still had issues with leakage and other various atributes of the process which is the main reason why Bulldozer runs "hot" and uses so much power.

Nice plug tongue.gifwink.gif
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post #35 of 51
Quote:
Originally Posted by jck;15309109 
Nice plug tongue.gifwink.gif

lol you tell me.. i never even knew they had a podcast..

@ tator tot i'll be looking forward to tomorrow's podcast.. thank's for the info
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post #36 of 51
Quote:
Originally Posted by Foxdie;15309251 
lol you tell me.. i never even knew they had a podcast..

@ tator tot i'll be looking forward to tomorrow's podcast.. thank's for the info
It should be out Sunday night; but I may set this one up to livestream if I can. I need to figure that out how to get that down first.

Hopefully, after I ramble, some people will have a better understanding of Bulldozer as a product.
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post #37 of 51
Quote:
Originally Posted by Tator Tot;15309106 
See, the article gives you that idea, but it's wrong.

Bulldozer Delays are almost entirely on Global Foundries 32nm process being bugged.

Like wise, Intel uses Automated design on their Sandy Bridge chips. They've been doing Automated Design on most chips since the Conroe days, 6 years ago.

Just because hand crafting/automated design didn't cause the delays doesn't mean that hand crafting as apposed to automated design would have caused things to take even longer.
post #38 of 51
I'm only a sophomore in electrical engineering, but knowing the basics of transistors can already help explain why having a 20% higher transistor count is an awful idea.

The reason why having more transistors is a bad idea is because transistors don't switch from on to off (and vice versa) instatneously. They have a contamination delay (minimum amount of time that it takes a transistor to switch states) and a propagation delay (length of time that a transistor stays in that state). They're measured in PICOseconds (1/100th of a nanosecond), but there's millions of transistors in a chip. Since there's so many transistors, these times will add up and mean lower performance. If there are even more transistors than necessary, then performance is even lower. It makes perfect sense from an engineering standpoint.
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post #39 of 51
@ Tator Tot: Listening to the Podcast right now, so far very good but I got a question for you if you don't mind.

The questions is, do you see your self with BD any time soon? Please explain.
post #40 of 51
Quote:
Originally Posted by Goatboy;15306983 
Sounds like a bad decision by management that led to a generally lackluster new processor series. Engineering decisions should be made by engineers, no one else.

Exactly^

U don't need a marketing department, if u have an over abundance of talented engineers. Their geekness alone solidifies a solid product.

Which in return, is how u first influenced investors. Now that you have people on the board of directors, a Company is no longer about it product.

It sometimes becomes about egoes.
Edited by formula m - 10/14/11 at 4:01pm
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