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[In] Why AMD Failed, Another Ex-Employee Confession - Page 10

post #91 of 177
The quotes in this article are old. Like months old.
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post #92 of 177
Quote:
Originally Posted by hajile;15355738 
It is unreasonable to expect the current generation of Bulldozer to beat Sandy bridge because it does not. (tautology FTW:D)
True, but it is reasonable to expect BD to beat a K10.5 on single-threaded processing. When else has a new architecture not beaten the precursor?


Quote:
Originally Posted by hajile;15355738 
Back to the topic at hand. There are many basic transistor circuits.These can be used to increase development speed, but just like in programming, using stock elements can lead to strange and hard to find errors.

Not yet discussed is the multiple layers of wiring for the circuits. Routing wiring correctly is very important to performance and yields. Bulldozer has a dozen or more layers of wire traces (edit: it seems like transistor count squares and transistor connections cube, but that's probably not quite accurate). Laying out billions of wires (each transistor has three wires) in a way that avoids problems (both more traditional and quantum mechanics related) is a problem that not only doesn't lend itself well to hand design, but isn't repeatable due to interconnections between various parts of the die and due to the die not being symmetrical (probably a symmetrical die would cause other even stranger problems).
I assuming "laying by hand" included traces as well.
Quote:
Originally Posted by hajile;15355738 
As to Intel designing completely by hand. This is not possible (for the reasons outlined previously). Intel may hand optimise more than AMD, but the majority of the initial layout is still done by a computer (thus proving once again that programmers are more important than engineers... unless the engineers are programmers:cool:).
Quitely bluntly, Intel probably has hired some of the best engineer/programmers and have larger skillsets than AMD.
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post #93 of 177
Quote:
Originally Posted by l1o2l;15351633 
My major is computer engineering... gotta help out AMD asap I graduate ;D

I do not give much stock to the article, because it is from the perspective of an ex-employee that wants to be anonymous. Ex-employees that want the company to succeed would speak openly about what they would like to see AMD do to perform like they had in the past, and don't bad mouth us agreements rarely last more than 6 months except for senior management.

That said, with all due respect, you are the guy this anonymous engineer is suggesting ruined the company. tongue.gif
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post #94 of 177
Quote:
Originally Posted by bru_05;15355919 
I said the design was for a server environment. I didn't say anything about the performance....

Uh, how is the design not directly related to performance?
Quote:
Originally Posted by bru_05;15355626 
Aren't these are server chips overclocked and ported to the desktop. I think the design is much better suited for servers and doesn't translate well to certain PC/Gaming uses. Whether or not they can be optimized, improved, revised, etc will remain to be seen. Hopefully they can with a revised BD or Piledriver or whatever is the last processor they release for AM3+ ha, I don't want to switch mobos and rebuild again for awhile. (well I do, but the lady would not approve:()

It seems those comments are in fact directly related to performance (or lack-thereof) of desktop BD. So let's get this straight - you haven't seen benchmarks, you haven't searched for actual data regarding your assertions - how can we take anything you say seriously?
post #95 of 177
Quote:
Originally Posted by Iceman23;15355982 
Uh, how is the design not directly related to performance?



It seems those comments are in fact directly related to performance (or lack-thereof) of desktop BD. So let's get this straight - you haven't seen benchmarks, you haven't searched for actual data regarding your assertions - how can we take anything you say seriously?

Man you do not like me...

To me it seems the 2 core per module and sharing of resources in the module is better suited for servers moreso than a typical desktop PC. FX BD does well in certain applications that are multithreaded, but for typical desktop uses and gaming it is not as good. I have seen benchmarks of FX BD but not of Interlagos.

I think you are misunderstanding where I am coming from. I am saying on paper the BD design looks like it would be more beneficial in a server environment. But, as I said before, I have not seen benchmarks for Interlagos. I was referring to server performance the whole time...
    
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post #96 of 177
Quote:
Originally Posted by DuckieHo;15355954 
True, but it is reasonable to expect BD to beat a K10.5 on single-threaded processing. When else has a new architecture not beaten the precursor?

I assuming "laying by hand" included traces as well.

Quitely bluntly, Intel probably has hired some of the best engineer/programmers and have larger skillsets than AMD.

The most outstanding example of architectures not performing as well as previous is the P4. When P4 launched (remember back) IPC dropped by 20% IIRC (vs 9% for bulldozer if Anand got it right) and the increase in frequency was nominal resulting in a processor which beat the previous generation by just a couple of percent (once again similar to bulldozer).

Laying billions of traces in a 3D space is impossible by hand. Even if one only assumes 1 billion traces (a 5 year timespan at 2000 hr/year), and that traces could be laid down at a rate of 1 trace/sec, the total engineer count would be 28. There's some problems here though. Even a minor redesign (not a completely new design, but greater than a minor stepping which is likely just tweaking existing transistors and traces by a little to improve performance and yields) require major rerouting for all traces and minor redesigns happen at least one time per year. This raises the engineer count to 140. Reduce the number of traces per minute to something more reasonable (probably 2-5 when factoring in time to consider consequences of placing trace in a specific place and time for minor reroutes of already placed traces, but not allowing for large errors which require rerouting of large areas) and the numbers skyrocket to (assuming 5 trace/min) 1700 engineers for designing trace layouts by hand.

Laying out traces with a computer would probably take a couple of weeks per revision. After each revision, a group of engineers with knowledge of both electrical engineering and fab engineering (a subset of chem engineering if I am not mistaken) would be need to tweak the design for optimal performance for a specific fab process. This group of 10-15 engineers and 5-10 programmers would accomplish far more in less time.

Faster iteration would make testing easier and make bugs more apparent. Considering that the bug report for Bulldozer (posted elsewhere on this site) is several times shorter than the one for Sandybridge, it seems that AMD did a better job of reducing computational errors even though performance is not good/terrible. If this reduction is due to AMD using computer designs rather than hand designs, I can't see too many problems here either.

I have little doubt that Intel hires the best engineers possible. I also do not doubt that AMD does the same.
post #97 of 177
Quote:
Originally Posted by Munkypoo7;15351936 
Lets not use blanket statements k?

I'd love to see your 5770 fold greater than it's nVidia counterpart.

Everyone has different uses for their cards, no one company is better than the other, else there would only be one company.

you mad ?? why the 5770 argument ??

since 5 series, amd/ati is crushing nvidia in sales, and in high end performance (6990 is better than 590)...that is a fact not an opinion
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post #98 of 177
Quote:
Originally Posted by DuckieHo;15355409 
It is unrealistic to expect a new design that is 6-7+ years in the making to beat a CPU based on a 8 year old architecture?

Fixed.
post #99 of 177
Quote:
Originally Posted by hajile;15356241 
The most outstanding example of architectures not performing as well as previous is the P4. When P4 launched (remember back) IPC dropped by 20% IIRC (vs 9% for bulldozer if Anand got it right) and the increase in frequency was nominal resulting in a processor which beat the previous generation by just a couple of percent (once again similar to bulldozer).

Laying billions of traces in a 3D space is impossible by hand. Even if one only assumes 1 billion traces (a 5 year timespan at 2000 hr/year), and that traces could be laid down at a rate of 1 trace/sec, the total engineer count would be 28. There's some problems here though. Even a minor redesign (not a completely new design, but greater than a minor stepping which is likely just tweaking existing transistors and traces by a little to improve performance and yields) require major rerouting for all traces and minor redesigns happen at least one time per year. This raises the engineer count to 140. Reduce the number of traces per minute to something more reasonable (probably 2-5 when factoring in time to consider consequences of placing trace in a specific place and time for minor reroutes of already placed traces, but not allowing for large errors which require rerouting of large areas) and the numbers skyrocket to (assuming 5 trace/min) 1700 engineers for designing trace layouts by hand.

Laying out traces with a computer would probably take a couple of weeks per revision. After each revision, a group of engineers with knowledge of both electrical engineering and fab engineering (a subset of chem engineering if I am not mistaken) would be need to tweak the design for optimal performance for a specific fab process. This group of 10-15 engineers and 5-10 programmers would accomplish far more in less time.
Forgot about Netburst....doh.gif

I wonder if AMD use their GPUs for 3D visualization of traces. biggrin.gif

The initial design is absolutely by computer. Refinements are made by hand. Today, what stepping is BD at?

Quote:
Originally Posted by hajile;15356241 
I have little doubt that Intel hires the best engineers possible. I also do not doubt that AMD does the same.
From my understanding, I believe Intel has multiple architecture teams running simutaneously around the world while AMD has few teams. Wasn't one reason for BD delay caused by resources being pulled off it? Intel had massive set backs due on the multi-billion Larrabee and that did not affect their near-term x86 timing.
Edited by DuckieHo - 10/18/11 at 11:35am
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post #100 of 177
Quote:
Originally Posted by DuckieHo;15356405 
I wonder if AMD use their GPUs for 3D visualization of traces. biggrin.gif

Today, what stepping is BD at?

B2 with rumors of B3 stepping sometime next year possibly in other models of the family that haven't launched yet.
Quote:
Originally Posted by DuckieHo;15356405 
From my understanding, I believe Intel has multiple architecture teams running simutaneously around the world while AMD has few teams. Wasn't one reason for BD delay caused by resources being pulled off it? Intel had massive set backs due on the multi-billion Larrabee and that did not affect their near-term x86 timing.

Correct in regards to multiple architecture teams displaced around the world (ex Israel , Oregon ...). AMD's architectural teams are limited to Dresden,Markham, and USA.
Edited by 45nm - 10/18/11 at 11:38am
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