Originally Posted by Artikbot
What you call your humble opinion has a crapload of sense.
When increasing NB speed all we do is bump the memory<->processor bandwidth and speed while keeping the same latency.
If that alone is a HUGE change (in PhII it was too), now cut latencies by a 25% and you get even faster links. Then a quadchannel IMC would make sense, and would skyrocket performance.
That wouldn't do anything for BD though, the NB clock does nothing for it as it is now.
The cache's latency is too high, not the speed.
Originally Posted by Rommel
Very true, and bd-e(?) should hopefully fix this, but you can't expect an enormous gain from it. Significant, yes, but i wouldnt say it would put it much past PH II single-core performance, which would basically just make it a Thuban x8. (4.5-5ghz though which might actually be pretty cool)
Either way, once they have more die space to play around with, be it through optimizations, cutting down on unneccessary cache, die shrinks, or something else, i think we'll see a really killer arch.
Yeah, it's up to GoFlo to fix their 32nm process, that's what's crippling BD as much as anything now.
The latency, (Cut L3 cache altogether, it does nearly nothing for desktop in AMDs own words and make L2 cache two separately accessed 1MB chunks per module rather than one 2MB chunk per module) the decoder (Even 6ops/cycle which would match Thuban when both cores are pegged), the size (Double the L1 cache to 32KB, or even quadruple it to 64KB) and fix the process. (Meaning it'll hit higher speeds, which is the point of BD).