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[Xbit] AMD Set to Unveil New Strategy Next Week - Page 15

post #141 of 143
Quote:
Originally Posted by Brutuz View Post
The power consumption has been going down quite a bit recently, it started off horrendously and now it's not so bad.

The L2 cache latency is over quadruple that of the L2 cache latency in a SB, and the L1 Data cache is only 16Kb per core (ie. 8x16=128KB total)
Wanna know the last CPU to come out with 16KB L1 data cache? The Pentium II.

Now, what proof do you have of the 32nm process and cache not being a problem for BD?
idk llano cache seems to be fine.
you just see to ignore that.
    
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post #142 of 143
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Originally Posted by Demonkev666 View Post
idk llano cache seems to be fine.
you just see to ignore that.
...Erm, Llano is a completely different chip, based off Deneb? What does it have to do with Bulldozer?
    
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post #143 of 143
Quote:
Originally Posted by radaja View Post
thats what so funny about abinsteins post,his new excuse is BD should have been a 3.0GHz with turbo of 3.5GHz and then power draw would be fine,it's just that us consumers wanted too much clock and it's our fault,and the real bad numbers in the reviews are the reviewers fault for clocking them up to 4.5GHz to 4.9GHz and complaining power draw is high
I wonder if abinstein realizes that you can take a Netburst dual core, run it at 1.2ghz, super-undervolt it, and get fabulous efficiency as well

I'm sure he never addressed why SB can hit higher than "expected" clock speeds and still operate within good power envelope. Nor did he address why AMD focused so much on breaking clockspeed records, if BD was designed as a low speed efficiency chip...
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