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Why are the second gen i5/7 processors clocked so high? - Page 2

post #11 of 12
Quote:
Originally Posted by DayoftheGreek View Post

A lot of the answers in this thread are spot on. The answer to your question in a combination of them.
If you look at a processor, it can only do so many things in one clock cycle. A processor can't do tons of things at once while simultaneously having a fast clock speed. It is a trade off. If you do a lot at once, each cycle of the clock generates a lot of heat and limits the clock speed. If you don't do a lot at once, you can afford a high clock speed to compensate. The art in processor design is finding a sweet spot that maximizes performances. Also, every time you make transistors smaller, less heat is generated per clock cycle. That enables you to make a processor with more instructions per clock, higher clock speed, or a combination of the two.
The problem with high clock speeds (no matter the processor design) is that you run into physical limitations of silicon that complicate things. You need to pull out some neat tricks in both CPU design and silicon refining and construction to overcome these problems. This is why you don't see any processor with very low instructions per cycle and very high clock speeds.
On top of all this, you have to make money as a company. Picking a design that has a high fabrication success rate makes you more money!

Exactly.

Having a Pentium 1 running at 6 ghz wouldn't be as great as you'd expect just because the frequency is higher. It would be absurdly limited/bottlenecked by cpu instruction sets/architecture.
Edited by Ascii Aficionado - 11/15/11 at 4:47am
 
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post #12 of 12
typically, in comp architecture, core clock speed is determined by the worst case execution time slowest stage in the pipeline.

for example:

If you have a Five stage pipeline (not very typical to have a 5 stage pipeline these days)

Stages:

Instruction Fetch (5 ps)
Instruction Decode (250ps)
Instruction Execute (300ps)
Memory Access (5 ps)
Register Write (1 ps)

so if you look at the timings above, even though the IF, MA, RW stages are so much faster we are still limited by the time at which it takes the execute stage to complete. therefore, the core frequency of the processor must be adjusted so that the instruction execute stage can be completed within one clock cycle..
f = 1/(300 ps) = 3.3Ghz

Typically what will happen most times is pipelines will have more stages which take shorter time periods to complete, therefore allowing frequencies to be much higher..
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