If you're an absolute novice, then you may want to start out using this simple guide:
before you take a look at some of the deeper settings I outline below.
Upon entering UEFI BIOS, we navigate to the AI Tweaker menu:
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Load Normal/Gamers/Extreme OC Profile: Each of these settings contains a pre-set that sets system bus frequencies and voltages for a quick starting point if you’re new to overclocking. The Normal profile will overclock your CPU to 4.375 GHz, the Gamer profile to 4.7 GHz. The Extreme profiles are for users that are utilizing Sub-zero cooling or chilled watercooling as both will set processor frequency at around 4.9GHz. With all of these profiles, active cooling of the onboard heatsinks is required.
Ai Overclock Tuner: Options are Auto, Manual and X.M.P.
Auto: This is the default setting, and needs to be changed to Manual if you wish to change BCLK (BCLK is the base reference frequency from which processor and other system bus frequencies are derived).
X.M.P: Extreme memory profile, use this option if you have Sandy Bridge qualified XMP memory. X.M.P. profiles contain pre-sets for system buses and in some cases voltages. If the specified speed of the DIMMs is greater than the supported memory frequency of the platform, a platform specific X.M.P. profile option becomes mandatory because processor core and memory controller voltage requirements vary from architecture to architecture. High-speed enthusiast memory kits manufactured before the inception of the Sandybridge platform may not contain the necessary/adequate voltage offset settings for the system to be completely stable. In such instances, manual adjustments of memory controller voltage and memory timings may be necessary.
Selecting the X.M.P setting opens up options for X.M.P profile selection (the kit may contain more than one X.M.P profile), and also opens up the BCLK option for changing system bus frequency. Note that memory operating frequency and maximum CPU operating frequency are shown towards the top of the Ai Tweaker menu, while memory timings and voltage are displayed next to the XMP profile selection box.
CPU Level Up: Allows us to select a pre-set profile that contains voltage and bus adjustments to apply a mild overclock to the system. Use this setting if you do not wish to overclock the system manually.
BCLK Frequency: This function becomes available if X.M.P or Ai Overclock Tuner “Manual” are selected. The base BCLK frequency is 100MHz. The CPU core frequency is derived via multiplication with the Turbo Ratio setting (final frequency is displayed at the top-left of the Ai Tweaker menu).
Bear in mind that the adjustment margin for this setting is not large - most processors have a range of 7 MHz +/- the base frequency. For example, if using a CPU Strap setting of 100MHz, then the approximate maximum BCLK for some CPUs is 107.0 MHz. If using the 125 MHz strap, then we’d expect a maximum in the 130 BCLK range.
CPU Strap: This setting multiplies BCLK to increase CPU frequency asynchronously from all other bus frequencies giving us more granularity to maximise processor and memory overclocking. Available settings are 100, 125, 166 and 250 MHz. For most CPUs the usable “straps” are 100 and 125 only. If using 166, try starting at 155 and see if the board will POST. If not, then you are likely limited to using 100 and 125 only.
Clockgen Full Reset: Re-initializes the on-board clock generator when bus frequencies or multipliers are changed. A setting of Enabled is recommended for all normal syste use. Disable only to experiment with memory stability when making changes to BCLK.
Turbo Ratio: Options are “Auto”, “By All Cores” and “By Per Core”. A description of these settings is provided in the right-hand column of the UEFI BIOS and can be seen when the Turbo Ratio setting is selected. Note that if overclocking past 4.5GHz, it can be beneficial to turn disable the Anti Surge Support setting in the Monitor section of UEFI to prevent power shut-off due to Super IO polling.
By All Cores: This sets the CPU core frequency multiplier; multiplied by BCLK to give the target CPU frequency (under full load conditions if SpeedStep is active). “Auto”: Stock CPU multiplier Ratio used. Manual numerical entry of the desired Turbo Ratio is accepted.
Per Core: Allows setting the maximum Turbo multiplier of each physical processor core.
The available multiplier range is limited by both processor model and the ability of each CPU.
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CPU Clock Gen Filter: A setting of Auto is recommened for most overclocking. For memory speeds over DDR3-2200 use 10UF, for speeds over DDR3-2400 use 20UF. If using the 166 strap then a setting of Disabled is recommended.
Memory Frequency: “Auto” will automatically select a memory multiplier ratio according to memory module SPD (Serial Presence Detect). Manual selection of the available memory frequency multiplier ratios is possible and works according to the abilities of the DRAM and processor. Granular control of memory frequency is available by manipulating BCLK, while the base frequency of each divider is offset by changing the CPU strap settings (within functional limits).
EPU Power Saving Mode: When “Enabled” is selected, utilizes power phase management based upon system loading to reduce system power consumption. A setting of “Disabled” is recommended for heavy overclocking.
DRAM Timing Control: Takes us to the DRAM timing sub-menu, where all primary, secondary and tertiary memory timings can be set:
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Load Elpida Hyper/ Tight PSC/Loose PSC RAW MHz Profile:
These profiles contain presets for the entire DRAM timing section and allow quick setup to facilitate overclocking or benchmarking. If you are using PSC or Elpida Hyper based modules, then try these profiles as a starting point. If overclocking with 64GB of memory, then using the RAW MHz Profile may be beneficial if you are experiencing any instability.
Rampage Tweak: A setting of Mode 2 is recommended for overclocking memory over DDR3-2000 or if using 64GB of memory.
Memory timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to make manual adjustments, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCSA and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings.
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP.Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD especially as Intel's newer processor architectures feature extensive reordering optimizations.
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
Latency Boundary: Use a setting of Nearer for most modules. For older DRAM ICs a setting of Further may be beneficial.
DRAM RAS to RAS Delay:Also known as tRRD (activate to activate delay). Specifies the number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.
Edited by Raja@ASUS - 12/20/11 at 4:27am