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[WCCF]Intel Ivy Bridge-EP Xeon with 10 Cores/20 Threads, 30MB L3 Cache Spotted Intel Ivy Bridge-EP Xeon with 10 Cores/20 Threads, 30MB L3 Cache Spotted - Page 7

post #61 of 79
Quote:
Originally Posted by gplnpsb View Post

In Sandy/Ivy cache design, the associativity is related to the size of each core's block of the shared cache, not to the total size of the cache.

This is a good point.
Quote:
Originally Posted by XPD541 View Post

I thought it was fake when I saw it running Windows 8, as evidenced by the ugly new "Start" button. My experience with Windows 8 is that anything more than 2 cores with HT makes the whole operating system unstable. Not sure if that was ever fixed, but the system WAS designed to run on tablets/mobile phones. But if it is real, then we will see it again, I am sure.
Personally, I believe it to be fake. wink.gif

There have been many builds of Windows 8 released since the developer preview. Also, x86 Windows 8 wasn't really designed for phones, the kernel it uses seems to be a direct evolution of the current NT kernel.

The images may well be fake, but thats sort of beyond the point.

There will almost certainly be 22nm Ivy based Xeons at some point.
Quote:
Originally Posted by Ha-Nocri View Post

what could the price be, approximately? I have no idea what a server chip costs....

Current 10-core Xeons are 4,000-5,000 dollars.

A 10-core ivy-ep, if released on LGA-2011, will probably be less expensive, but I would not expect much less than $2k a chip.
Edited by Blameless - 2/4/12 at 1:44am
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post #62 of 79
The only reason the current 10 core Xeons cost that much is because they are -EX Xeons, which command a price premium obviously. When the 10 core pseudo-mainstream EP Xeons are out, there will likely be 12 or more cores on the -EX Xeons. I'm sure the IB-E EP Xeons will cost about the same as the SB-E Xeons will, which is somewhere in the $400-$2000 range depending on what core count and clock speeds you want.
    
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post #63 of 79
bla bla bala... I think fake! Looks like Intel use Nvidia PR policy
post #64 of 79
Quote:
Originally Posted by mkclan View Post

bla bla bala... I think fake! Looks like Intel use Nvidia PR policy

why would it be fake? It's perfectly believable that Ivy Bridge-EP is a native 10-core when Sandy Bridge-EP is a native 8-core.
 
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post #65 of 79
    
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post #66 of 79

Yeah I admit that some of the info is kind of off, but that's nothing new. Pretty much every time we see first CPU-Z shots of an upcoming CPU, especially a non consumer class one it's riddled with incorrect numbers etc. Core/thread count are often the only ones that are somewhat reliable.

And as I said a native 10 core makes sense for IB-EP
 
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post #67 of 79
Hmm... maybe if I start saving now I can afford it by 2050 biggrin.gif
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post #68 of 79
Quote:
Originally Posted by Alatar View Post

Yeah I admit that some of the info is kind of off, but that's nothing new. Pretty much every time we see first CPU-Z shots of an upcoming CPU, especially a non consumer class one it's riddled with incorrect numbers etc. Core/thread count are often the only ones that are somewhat reliable.
And as I said a native 10 core makes sense for IB-EP

There are definitely issues with CPU-Z recognizing new CPUs, but in my experience the extended family and extended model info should be correct. They're simply read out of the CPUID 8000_0001 EAX register. Cache information can be off, but the cache on my SNB-EP is recognized properly since CPU-Z 1.46. That version is from June 2008, a year before even client Sandy Bridge taped out. The first version to show associativity, 1.52, recognizes the associativity of SNB-EP cache correctly. It's from July 2009, a year before the first SB-EP 8C/16T screenshots of A0 silicon began to leak out. My point is that For Ivy Bridge-EP, which is based off a known architecture, recognition of Family, Model, and cache information should occur without problem, just as it does for client Ivy Bridge.

I agree that 10C/20T makes sense for IVB-EP. I wouldn't be surprised by an upgrade to 3MB/L3 per core, or even by a 12C/24T IVB-EP die. I'd even bet that there will be at 16C/32T IVB-EX die, based on this resume of an apparent chip architect. It appears legitimate, as this guy holds a number of patents issued to Intel. Here is a quote: "Currently involved with Multisocket validation/ Emulation of 16-core Ivybridge Server processor product.". My own estimates indicate that such a die should be possible in 500-600 mm2 at 22nm, even with 3MB or more of L3 per core. (At 32nm, a 16-Core SNB-EP based processor w/ 2.5 MB of L3 per core would be around 650mm2). A die size of 500-600 mm2 is quite in line with current -EX dies. Nehalem-EX was 684 mm2, and Westmere-EX was 513 mm2.

This is a photo showing how CPU-Z recognition has progressed for SNB-EP.

627
post #69 of 79
OMG the folding that beast could do!
post #70 of 79
Quote:
Originally Posted by mam72 View Post

People are surprised that this is fake, its off WCCF most of the stuff there is fake.
OP is the guy on WCCF he just wants hits on his website. This is starting to get annoying he should be posting in the rumour section and this isn't the first time he did this.

The actual source is coolaler, who has generally been credible in the past but apparently faked the first IB-E screenshot.
    
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Overclock.net › Forums › Industry News › Rumors and Unconfirmed Articles › [WCCF]Intel Ivy Bridge-EP Xeon with 10 Cores/20 Threads, 30MB L3 Cache Spotted Intel Ivy Bridge-EP Xeon with 10 Cores/20 Threads, 30MB L3 Cache Spotted