[PC Per] Collision alert! ARM, AMD and Intel are all headed for the same market... - Page 3

And ARM doesn't? The x86 architecture is not RISC even in the slightest, it was designed as a CISC chip, and it stays a CISC chip. There are ARM microcontrollers with TDPs in the micro-watt range as well. Also, how is MIPS without baggage? Power consumption may have risen with each new generation of ARM chips, but performance increases greatly*, also there are solutions that ARM Holdings has made to allow for these higher power, high performance cores. For example the ARM Cortex A15 "Eagle" has a smaller, more power efficient core that execution can be switched to when needed. There is a company that's going to put an ARM chip on the market with hundreds of cores. i.e. MIPS is nothing special in the world of RISC



*performance increases are gained by uping the clock speed or improving the on the architecture. In the case of the latter, it can be used to cut power consumption or gain computing power. In the case of the newer ARM designs, it appears that the goal was to keep power consumption nearly the same but up clock speeds and make architecture changes. This seems likely to be preparation for ARM holdings to directly compete with Intel in the laptap/desktop market.
Edited by lin2dev - 2/12/12 at 5:38pm

And ARM doesn't what?

I never said ARM was a bad architecture (nor did I say x86 was a bad architecture) Edit: I am using the term "architecture" but would be remiss if I didn't point out that they are instruction specifications, and just like specifications for a block of code in a program doesn't necessarily specify how it must be implemented, so most instruction sets don't specify most hardware methods. ARM using A15 and A7 chips in big-little configuration is somewhat irrelevant to the conversation however interesting I find the concept to be (I've been thinking about the overall efficiency of that method for a couple of months now). According to Anandtech, Medfield beats dual-core A9 chips in idle power consumption. This seemingly strange reverse of rolls leads me to believe that big-little may be an unnecessary concept.

x86 is currently implemented via a RISC ALU. Notice in the pictures below how the decode stage is before the instructions are executed. Current x86 designs work by breaking down the incoming instructions (note: some instructions are single instructions identical to what would be found in ARM or MIPS) into macro-ops or micro-ops. Macro-ops are where one CISC instruction is broken down into two or more individual instructions (individual instructions being the micro-ops). Macro-ops are left together (in architectures such as Bulldozer) until just before execution because moving one large chunk of instructions is faster than moving all the little parts. Upon reaching the ALU, they are broken down again into micro-ops for RISC style execution (assuming that they weren't single micro-ops to begin with). This is why I am correct when I say that modern x86 is a RISC architecture with a CISC front-end (which decodes instructions into RISC instructions).

MIPS is very special as far as architectures go if only because it is the only architecture made to be technically perfect without need to produce results (ie, a bunch of university experts got together and decided to create the best architecture they could. After they were done, on of them got the brilliant idea that maybe someone could actually use the revolutionary design, so said researcher left the university fold to create the company now known as MIPS). If you want a bit of technical reading, read the papers on MIPS-X (the second generation MIPS designed after Hennessy left the Stanford team).

MIPS doesn't have a lot of cruft because the instructions are so simple that they don't need changing (the only changes have been adding the occasional instruction and the 64-bit instructions), thus there isn't much baggage to speak about (while ARM has baggage such as having only half the amount of registers available in a MIPS chip making compiler optimization much harder). MIPS is true RISC while ARM has taken on some very CISC-like tendencies with several instruction sets. When the Chinese government looked at all the architectures they could find in order to start their own chip-making venture, they chose MIPS. This wasn't due to cost (they didn't strike a deal with MIPS until they were years into their Loongson project), but instead was because their scientists said MIPS was the best.

ARM is introducing a 64-bit architecture (21 years after MIPS and rumored to be *very* similar), but the design doesn't hit for a couple of years (after A15). In the meantime, MIPS makers have had years of practice and experimentation making powerful chips (MIPS used to power several of the fastest supercomputers once upon a time). I am familiar with embedded ARM (specifically the M0-M4 series of microcontroller designs). My point was that MIPS currently (ie now, not a promise to have in the future) has designs that scale from extremely low power to very high performance (side-note: one of the big competitors to the M0 is the old CISC 8052 designed by Intel). You mention an ARM licensee making chips "with hundreds of cores". I would love to know who as I am interested in the design.


Edited by hajile - 2/12/12 at 9:55pm

I got devices that run on x64, x86, & ARMv7. AMD, Intel & ARM Must love me LOL

It seems likely that the current A9s are fabbed in 45nm, which is more power hungry, also AnandTech is comparing a single core chip(?) to a duel core chip, is there numbers listed? Also, the ability to switch endianess can just be as simple as swaping byte order as it comes through, the circuitry for that would take minimal power . As for the massively multi-core chips it appears that it is multiple chips on one system, the article can be found here: http://www.pcworld.com/article/221910/calxedas_arm_chips_designed_for_480core_servers.html
I recalled it wrongly from memory , but this is a reasonable proof of concept, although a single chip with more than a handful of cores with each having the complexity of an A9 or A15 would have some yield problems

The definition of a CISC architecture is a variable instruction set that takes many cycles to execute. A RISC architecture doesn't have a complex decode, the instruction set consists of what CISC architectures decode to. Whether an architecture is CISC or RISC depends on the decode stage, not the execution unit or ALU.
Edited by lin2dev - 2/13/12 at 12:54am

x86 is still trying to scale down into the sub 2w market for tablets and smartphones, ARM is already well within there. Hence, ARM can keep the power consumption stable while x86 has to lower it. And Medfield isn't all it's cracked up to be either, Intel's comparison was against what will be out-dated CPUs by the time Medfield is actually on the market, it's like comparing Zambezi to Conroe back in 2007, sure, Conroe is what we had then but when you compare it to Nehalem and Sandy Bridge it really falls down and pales in comparison.

Medfield looks great for tablets (Apart from the high power consumption) but by the time its out, I doubt it will be so great.

Every newer x86 chip is RISC internally, but with a decoder for the CISC x86 instructions. Hence, you're both right, the x86 architecture isn't RISC but all of the modern x86 CPUs are internally.

The issue is DRIVERS. Beagleboard for instance has full support in .c files outlining how the DDR controller / GPIO / SPI / USB / Serial are connected to the CPU/mainboard. Phones don't always have these available to Ubuntu devs (unless they are open source android). You generally also need some kind of U-Boot support to physically load the Ramfs / Initrd / vmlinux files.

So...people need a "guide" on how things interact in each environment to know how to code for it? And since the makers don't provide that then they have to trial and error it? Gah...I wish I could wrap my head around this.