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Trend of low frequency/ High Multipliers: What limits have people explored?

post #1 of 5
Thread Starter 
I am very curious as to the extent people have taken this concept to.What is the Lowest Frequency you can seeably go? I do not own a SNB yet, but I aspire to... So I have no experience with them personaly, but I am interested in the concept, for efficiency purposes. Are the cores totaly unlocked, no limit to multiplier or frequency by limits in BIOS?

If some people could post a few examples of how far you have gone. I'm looking at blocks in say the 50bclk x 100 for a 5.0Ghz tune, or even a 55x100 for 5.5Ghz... or 70x90 for 6.3Ghz.. 80x80 for 6.4Ghz... What voltage range would these specific tunes require if viable?

I see it in a nuts a bolts kind of way... If there is efficiency gain by going in a direction of lower frequency and higher multipliers, what is the limit for a given chip design? I mean in a communications way... If the freequency is lower its rate of data movement is slower (as i gather it), so in order for data to move quickly at a lower rate the distance of travel mus be reduced... So this is only a plausible example as die sizing reduces to an exceptable range for said frequency ranges to be useable in a "litteral" sense. You can have the overall frequency, but it doesn't get to where it's going in a timely enough manner because the distance is too far to travel, what good would it do? If you get what I mean, and providing I am viewing what is going on from the right perspective.

I see it like a low RPM motor with lots of Cylinders this way... You lower the operating requency to a point where you can back off the voltage (For a given over all CPU frequency), yet you gain the advantage of mutiple cylinders with the higher multiplier. Like runnin a big motor at low RPM... which is best for moving a high amount of "work" at a given time...

So what is the limits of this particular series in terms of maximum attainable frequency and effieciency with lower frequencies and higher Multipliers? What are some examples you can through at me?

And secondly am I viewing this concept correctly?
Edited by gtfoxy - 2/17/12 at 5:14pm
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post #2 of 5
Depends on the chip bud...I'd stay under 1.55v but that should be more than enuff for 5GHz.
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post #3 of 5
Thread Starter 
Quote:
Originally Posted by PROBN4LYFE View Post

Depends on the chip bud...I'd stay under 1.55v but that should be more than enuff for 5GHz.

If you could give me some numbers you have used that would be cool... What have you used as a maximum multiplier?
Edited by gtfoxy - 2/17/12 at 5:22pm
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post #4 of 5
You cannot do any of those "tunes" you want to.
First of all the BLCk is tied to the DMI and PCI-E clocks, you cannot get your CPu to do more than 110blck or less than 90blck, you are stuck in that range. More so I don't expect you to be able to easily stabilize over 107mhz BLCK, and only certain chips can do 110, or even 107 is hard. PLus changing the BLCk hurts the CPU in the long term.

As for clock walls you cannot go higher than 6ghz, infact that is the world record of Sandy Bridge. its just multiplier with SB.

in general however higher multiplier and lower blck or visa versa should show no real performance difference, infact higher multiplier and lower bus does seem to yield better results on X58 such as in superpi benchmark. But higher bus and lower multiplier seemes to do better in cinebench. The difference really you wont see. On SB, just use 100mhz.
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post #5 of 5
Thread Starter 
Ok, so they give a tighter frequency range, got it.

Does modulation control have much to do with this limiting of frequency? Do you see a wider range of frequency adjustment in the upcoming IB series?

You hit on something I have observed; the relationship between bclk/ overall cpu frequency & certain types of processing chores. Seems this is showing the difference as to the chipsets from AMD & intel directly, as well as indirectly, when comparing their various rendering styles of their supporting platforms & the types of games they play better/ worse in.
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