A BIG THANK YOU! to TheJesus who has been contacting both AMD and nVidia about the issues we are having getting to 120hz (also with SLI). Here is his post from another site w/the companies' respective answers:
Alright, Nvidia's real support has typed up quite the response. This pretty much states you're lucky the Kepler can do it, Fermi can't, and the actual SLI bridge forces the 400MHz pixel clock.
The case was escalated to me. The 330MHz pixel clock limit is true for Kepler and Fermi when using the dual-link DVI connection. If the connection is over HDMI/DisplayPort then there is a difference between Fermi series (225MHz) and Kepler (340MHz). I don't know the confirmed tested speeds of all connectors but I do know that it's possible to get it working beyond specification. But anything beyond the specification may or may not work depending on the monitor, and result will vary with different cards.
Looking at the EDID timing you provided for this monitor, a pixel clock of 400Mhz (399.84Mhz) would be required to reach 2560x1440@100hz and 500Mhz (497.76Mhz) for 2560x1440x120Hz. I'm surprise you are able to get this to work with dual-link DVI at all, unless you are over-clocking the DVI in order to get more bandwidth. I don't see any other way dual-link DVI would work since 120Hz would require a lot more than 330Mhz. Again I suspect depending on the board, it may be possible to get it working beyond specification, but the result will vary from board to board. Its like over-clocking, some boards will over-clock better than other boards. I've confirmed with engineering and current pixel clock for Kepler and Fermi is correct.
SLI is more timing sensitive so the timing enforcement will be more strict, this is by design to insure stability. The same is true for other GPU clock specifications when it comes to SLI. Take the GPU core or memory clock for example, in an SLI configuration if the clocks are different for each GPU then the software will always default both GPUs to the lowest common clock. Another word if one GPU was running at 800Mhz while the other was running at 825Mhz, as soon as you enable SLI both GPU will now run at 800Mhz. I suspect the strict timing requirement is likely preventing pixel clock to run any higher than the default.
Based on my understanding on the issue, and my discussion with engineering, I don't see anything that suggest a problem with hardware or our software implementation. If you're asking us to up the specification on our pixel clocks then I'm afraid that's not something we will do unless there is valid reason for it. These clocks are set after rigorous engineering calculations and testing, they are set at those levels for good reasons. As for the restriction when in SLI mode, that is by design and expected behavior. If I'm mistaken then please help clarify the issues.
Sorry, slight correction on my part with previous specification. The TMDS specification I listed below did not account for DL-DVI. The max, theoretical TMDS link clock is 225MHz for Fermi and is 340MHz for Kepler, which was derived from the HDMI SL requirements. So DVI DL, could go up to 450MHz on Fermi and up to 680MHz on Kepler. Note that these are all theoretical, the real values are determined during qual. Also note that the quality of cabling may be a factor beyond the standards limits.
The result you are reporting is in-line with the specification. Kepler is capable of the 2560X1440@120Hz but Fermi is limited to 2560x1440@100Mhz due to the 450Mhz. If you look at the monitor EDID detail timing the 24560x1440@120Hz would require 500Mhz, which Fermi is not capable of supporting. I've confirmed with engineering on these specifications.
Detailed Timing [DTD#1] 2560 x 1440 @ 120.00Hz Pixel Clock : 497.76MHz HBlank, HBorder : 160, 0 HSyncStart, HSyncWidth : 48, 32 VBlank, VBorder : 85, 0 VSyncStart, VSyncWidth : 3, 5 Image size : 640mm x 360mm DigitalSeparate +/-
Detailed Timing [DTD#2] 2560 x 1440 @ 100.00Hz Pixel Clock : 399.84MHz HBlank, HBorder : 160, 0 HSyncStart, HSyncWidth : 48, 32 VBlank, VBorder : 30, 0 VSyncStart, VSyncWidth : 3, 5 Image size : 640mm x 360mm DigitalSeparate +/-
And one more:
I just got confirmation from engineering that the maximum speed of the SLI bridge is 400Mhz, which would explain why this is limited while in SLI mode. So it's not so much the common timing but a limit on the SLI bridge.
And I also got this from AMD:
Response and Service Request History:
So, how exactly can we assist you on this issue. As I mentioned before there is a hardware limitation thru DL-DVI.
In order to update this service request, please respond, leaving the service request reference intact.
AMD Global Customer Care*