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[TPU] Ivy Bridge Temperatures Could Be Linked To TIM Inside Integrated Heatspreader: Report - Page 10  

post #91 of 387
To all those saying that this could be an engineering sample issue, we have already seen retail units being tested out in the real world and they have the same issues.

Now going back a step, I remember people saying that the E0 Eng. samples that were out there, performed much better than the E1 units, which is the retail stepping.

This being the case, could it be that the E0 had solder and the E1 has the TIM?

If this is the case, I think Intel seems to be pulling back their own CPU because this would give them another product to sell in the future...

I wish AMD BD had done well, then we would not have seen this crap happening..if this whole theory is true
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post #92 of 387
Composite polymer as the highest heat extraction.695 vs 400 for copper .dont know about you but this is huge.just going from copper to silver will rise your heat extraction to 426 more the 5% so you would gain around 5 degree all else being equal.so sadly from 400 copper to 695 composite polymer .the gap is so huge i am just surprised none often the replacement of stock heat spreader fror composite polymer
Edited by drbaltazar - 4/25/12 at 9:46pm
post #93 of 387
Hoping retail doesn't have TIM.


If retail does have TIM then IMO this is definitely intentional to protect SB-E and future cpu products.

I have a bad vibe about IB. Should have been fantastic but all leaks and review all point to a hot running chip. The TIM explains what can be observed by the eye but I wouldn't be surprised if Intel is holding off on improved stepping to keep improved revisions coming later on.


I agree with what others have said that everyone needs to let Intel know with their wallets that we are not pleased about what we are seeing.


Hopefully we are all just being a little paranoid about this and next week we don't see any TIM used on IB on retail processors.
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post #94 of 387
Quote:
Originally Posted by drbaltazar View Post

and the smaller proc get the higher performing the cooling solution will need to be

Actually this is the opposite of what engineers are striving for. As the technology improves, chips are being made more efficient and with higher performance per watt. This was a major benefit of Ivy Bridge with the move to the tri-gate transistor design to reduce leakage. The chips use less power and should therefore put out less heat while performing on par, or in this case slightly better than the previous generation.

I actually had a hunch a while ago that this might be the reason for higher than expected temps, as was the case with some of the core 2 line-up. I wondered if anyone had removed the IHS to check, but I ended up dismissing the theory in my mind thinking Intel wouldn't cheap out on such a high end part.
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post #95 of 387
Aside from here i doubt many have noticed this .even less if any will look into it.i could be wrong but it probably wont reach intel level of awareness.oh well time to go warm up my bed sheet .later guy .ty for all the good info .very nice
post #96 of 387
Quote:
Originally Posted by drbaltazar View Post

Aside from here i doubt many have noticed this .even less if any will look into it.i could be wrong but it probably wont reach intel level of awareness.oh well time to go warm up my bed sheet .later guy .ty for all the good info .very nice



I've been surfing my favorite computer WEB sites and all of them have people raising hell about this.
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post #97 of 387
how hard is it to pull off these heat spreaders? now I want to try this with SB lol
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post #98 of 387
Quote:
Originally Posted by cayennemist View Post

how hard is it to pull off these heat spreaders? now I want to try this with SB lol


Not really needed since it has a more expensive and proper fluxless solder. I'm sure it would lose resale value big time and probably void the warranty.
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post #99 of 387
Quote:
Originally Posted by coolhandluke41 View Post

O really ..?
this is what you will get ;
CPU Die -> 5 W/mK TIM -> IHS -> 5 W/mK TIM -> Heatsink/H20 block will be better
(lapping IHS paper thin=around 30% instead of 100% )+ no TIM (Indigo is supper thin=like liquid/after flow is solid )




You're either ignoring my point or you don't get it.



P.S.: If the connection between the IHS and the die is filled with cwap, lapping won't make a difference… I'm not talking about future chips that have proper TIM between IHS and die. I'm talking about these, so called, flawed chips. I know how lapping works with a "proper" chip...
Edited by Xenthos - 4/25/12 at 10:14pm
post #100 of 387
We spoke about this at the live stream launch party on Monday. I expect to see the more intense overclockers to start popping lids more often than previous generations, but most of us won't bother. I am also guessing that Intel's reasoning is purely financial in motivation and not to throttle or hinder the chips in anyway.
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