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[Xbit] Globalfoundries' Fab 8 to Enable 3D Stacking of Chips. - Page 2

post #11 of 21
IBM already dd it
post #12 of 21
Quote:
Originally Posted by FXLabs View Post

IBM already dd it

Show a source link to prove your point.
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post #13 of 21
Quote:
Originally Posted by Just a nickname View Post

Wrong, enjoy the read:
http://www.overclockers.com/ivy-bridge-temperatures
If the high power parts are close to the IHS it shouldn't be a problem.

The 3D this is talking about and the 3D that Ivy Bridge use are two completely different 3Ds:

IC Stacking:
DC1503_FEAT_2_PG_34.gif

"3d" Transistors:
Intel-trigate-i.jpg

As you can see, two completely different technologies. The "3d" on tri-gate transistors is kind of a misnomer, and really just a marketing ploy as "everything 3d is better" these days.

You can imagine, if you took an Ivy bridge die package and slapped it on top of another Ivy Bridge die package, and only put the top one in contact with the IHS (because the other one is covered up) you would very quickly see a rise in temperatures beyond limits.
    
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post #14 of 21
Quote:
Originally Posted by Xaero252 View Post

The 3D this is talking about and the 3D that Ivy Bridge use are two completely different 3Ds:
IC Stacking:
DC1503_FEAT_2_PG_34.gif
"3d" Transistors:
Intel-trigate-i.jpg
As you can see, two completely different technologies. The "3d" on tri-gate transistors is kind of a misnomer, and really just a marketing ploy as "everything 3d is better" these days.
You can imagine, if you took an Ivy bridge die package and slapped it on top of another Ivy Bridge die package, and only put the top one in contact with the IHS (because the other one is covered up) you would very quickly see a rise in temperatures beyond limits.

Okay that's good but what is your point sir?
I was replying to the post quoted as you can note smile.gif
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post #15 of 21
Quote:
Originally Posted by Xaero252 View Post

The 3D this is talking about and the 3D that Ivy Bridge use are two completely different 3Ds:
IC Stacking:
DC1503_FEAT_2_PG_34.gif
"3d" Transistors:
Intel-trigate-i.jpg
As you can see, two completely different technologies. The "3d" on tri-gate transistors is kind of a misnomer, and really just a marketing ploy as "everything 3d is better" these days.
You can imagine, if you took an Ivy bridge die package and slapped it on top of another Ivy Bridge die package, and only put the top one in contact with the IHS (because the other one is covered up) you would very quickly see a rise in temperatures beyond limits.

How is Ivy being marketed as using tri-gate transistors a ploy on using 3D? From your own picture I deduce a working transistor that now effectively uses 3 dimensions i.e x,y,z to perform its function.
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post #16 of 21
Quote:
Originally Posted by FXLabs View Post

IBM already dd it
Quote:
Originally Posted by Mr_Torch View Post

Show a source link to prove your point.
To note, this is not new technology... IBM and Samsung both have done it.

Stacked DRAM and CPU+DRAM are "common" uses.
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post #17 of 21
Quote:
Originally Posted by DuckieHo View Post

To note, this is not new technology... IBM and Samsung both have done it.
Stacked DRAM and CPU+DRAM are "common" uses.

It hasn't been mass produced though, has it? That's what GloFo is enabling here - mass production, right?
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post #18 of 21
Quote:
Originally Posted by Homeles View Post

It hasn't been mass produced though, has it? That's what GloFo is enabling here - mass production, right?

As I understand it, yes. It brings the tech out of special use, expensive production, into something slightly more affordable.
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post #19 of 21
Quote:
Originally Posted by Homeles View Post

It hasn't been mass produced though, has it? That's what GloFo is enabling here - mass production, right?

It just expands the number of companies that are equipped to do stacked chips. This will lead to more supply and lower prices. It will also increasing industry knowledge/experience on the technique leading to more implementation... increasing usage.... and more companies will offer it.
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post #20 of 21
Quote:
Originally Posted by DuckieHo View Post

Stacked DRAM and CPU+DRAM are "common" uses.

for example: http://beagleboard.org/hardware they stack Nand, CPU, RAM, and I believe the DSP/IGX, so its 4 levels. its Package On Package I believe.

Doing on die stacking would be even better.
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