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[MT] Intel Admits That Ivy Bridge Runs Hotter Because Of 22nm Shrink - Page 6

post #51 of 183
Quote:
Originally Posted by dr/owned View Post

I wouldn't bet my life on it, but I'm fairly certain that this is incorrect. If you want to hardcore thermal stress test something, you put a 70 pound block of copper on top of it. Huge thermal conductivity and huge thermal mass.

Nah, because beyond a certain point thermal resistance begins to act as an insulator. This the same principle behind why you apply TIM in small quantities, because too much of it insulates heat rather than conducting it on to the heatsink.
post #52 of 183
Quote:
Originally Posted by dr/owned View Post

A quick google shows that silver is only 5% better thermal conductivity than copper though. Probably not worth the cost/difficulty to acquire.

Without tampering you'd have a layer of TIM, a nickle plated copper plate, more TIM, another nickel plated copper plate, solder TIM, and then heatpipes.

Removing all of that and replacing it with a layer of metallic TIM (cool laboratory liquid pro or Indigo), a plate of silver, and one more layer of metalic TIM would likely improve total thermal resistance by more than 5%, mostly because the removal of extraneous thermal interfaces.

The silver (which would cost about 100 dollars) can easily be reused for another project down the road.
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post #53 of 183
Quote:
Originally Posted by eugenekrabs View Post

Does that mean 14nm will be even hotter?

It means, a smaller die space is harder to cool than a larger one.
Edited by PoopaScoopa - 4/30/12 at 12:02pm
post #54 of 183
Quote:
Originally Posted by Blameless View Post

[

Removing all of that and replacing it with a layer of metallic TIM (cool laboratory liquid pro or Indigo), a plate of silver, and one more layer of metalic TIM would likely improve total thermal resistance by more than 5%, mostly because the removal of extraneous thermal interfaces.

The silver (which would cost about 100 dollars) can easily be reused for another project down the road.

I was suggesting to replace only the silver portion of your scheme with copper. I assume the die is perfectly flat and smooth. If you press your shim between two gage blocks ($$$) it would also end up being perfectly flat such that you wouldn't need TIM (in theory) between the die and the shim. This also assumes your shim is polished to a mirror finish such that there's no micro pits.
post #55 of 183
I'm no processor engineer, and I know that my idea would lower profits, but how much performance would you lose if the dies were kept the same physical size as previous generation, with the cores spaced out more on the die?

This would at least solve the issue of having so much heat in such a small area, but at what cost to performance?
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post #56 of 183
they would lose a lot cause the more tightly they can pack,the more proc per waffer
post #57 of 183
Quote:
Originally Posted by kennyparker1337 View Post

A new stepping could fix it, but intel won't waste money on that unless it costs more than current stepping.
Most likely, Intel will release their "kick butt" Ivy Bridge next phase as Haswell. Just like Sandy Bridge was the "kick butt" phase of Nehalem.
What I'm saying is, if you got Sandy Bridge wait for Haswell at the very least. If you got anything before Sandy Bridge or ANYTHING from AMD, just go Ivy Bridge. It costs nearly the same, and will net you about 5-10% performance gain even when overclocking.
Haswell is not due for at least another 12 months.

Intel will absolutely have another stepping for IVB. Intel is experience growing pains with this immature 22nm process. As they get practice and the process matures, they will learn how to tweak the process to improve yields/leakage. This would warrant a stepping.

Quote:
Originally Posted by axipher View Post

I'm no processor engineer, and I know that my idea would lower profits, but how much performance would you lose if the dies were kept the same physical size as previous generation, with the cores spaced out more on the die?
This would at least solve the issue of having so much heat in such a small area, but at what cost to performance?
That will not work.

One reason for better performance is lower propagation delay.... it takes less time for electrons to move through the chip. If you space the transistors more, then you have to deal with higher propagation delay and greater chances of skew/noise. Then you would have to lower clocks or build additional circuitry to reduce the noise.... and you either get worse performance or a hotter chip.
Edited by DuckieHo - 4/30/12 at 12:07pm
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post #58 of 183
Quote:
Originally Posted by axipher View Post

I'm no processor engineer, and I know that my idea would lower profits, but how much performance would you lose if the dies were kept the same physical size as previous generation, with the cores spaced out more on the die?

This would at least solve the issue of having so much heat in such a small area, but at what cost to performance?
I imagine spacing them out leads to delays between the traces. There's crap like trace capacitance and all that but I didn't like my VLSI course so *shrug*
post #59 of 183
Quote:
Originally Posted by axipher View Post

I'm no processor engineer, and I know that my idea would lower profits, but how much performance would you lose if the dies were kept the same physical size as previous generation, with the cores spaced out more on the die?
This would at least solve the issue of having so much heat in such a small area, but at what cost to performance?

That might help a little bit, but still each 22nm core will be denser than a 32nm core and therefore run hotter even if they are spaced apart from one another. Seems almost useless honestly.

It seems as though 32nm was the sweep spot for heat dissipation. And until Intel finds a way to force the heat out of the densely packed 22nm cores better, they will remain hotter. It really isn't Intel's fault, it is thermodynamics fault.
Edited by icehotshot - 4/30/12 at 12:07pm
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post #60 of 183
Quote:
Originally Posted by kennyparker1337 View Post

A new stepping could fix it, but intel won't waste money on that unless it costs more than current stepping.
Most likely, Intel will release their "kick butt" Ivy Bridge next phase as Haswell. Just like Sandy Bridge was the "kick butt" phase of Nehalem.
What I'm saying is, if you got Sandy Bridge wait for Haswell at the very least. If you got anything before Sandy Bridge or ANYTHING from AMD, just go Ivy Bridge. It costs nearly the same, and will net you about 5-10% performance gain even when overclocking.

New steppings are an inevitable part of the manufacturing process. They wouldn't arbitrarily limit the refinement of their silicon if they can make better silicon less prone to error
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