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Explaining PLL.

post #1 of 5
Thread Starter 
Aight so I've been looking into the terminology for such CPU/BIOS options. PLL being one of my main interests atm since I would like to go higher than 4.5 GHz. So far what i understand from reading around is that:

The output waveform has to land/end on the starting node of a reference waveform. I get that it limits something, but not sure what it is "limiting". Another questions is, why is PLL measured in volts if it's more like a frequency? Correct me of wrong, just here to learn.

Thank you biggrin.gif
Edited by lpjz50 - 5/2/12 at 2:54pm
post #2 of 5
PLL is a feedback mechanism that keeps the distributed clock aligned with the reference clock. The reason PLL is measured in volts is because it is a voltage controlled oscillator. The quote is from wikipedia, and they have a good diagram to go along with it.
Quote:
The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.

I also suggest taking a look at this thread. they suggest that you don't need to change the PLL voltage until after the 56x multiplier.
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post #3 of 5
Thread Starter 
I looked at the thread and my last question is, how does increasing/decreasing the voltage affect the way it is distributed? BTW thanks those links help.
post #4 of 5
Quote:
Originally Posted by lpjz50 View Post

I looked at the thread and my last question is, how does increasing/decreasing the voltage affect the way it is distributed? BTW thanks those links help.

affect the way what is distributed? i'm not exactly sure what you're asking.

that thread had the best explanation i could find about the effects of changing the PLL voltage. but from what i've read, lowering the PLL voltage can improve stability when the multiplier is < 56x. and increasing PLL voltage can help when the multiplier is > 56x or the BCLK is increased.

everything i've seen on the internet says that no one really knows the exact internal workings of the PLL except Intel engineers. i think the best we can do is guess based on observations. you might be able to get a better grasp on it by looking at patents filed by intel. but i personally have no inclination to dig through patents today. tongue.gif
Quote:
By changing the PLL voltage at the CPU side, you are either making a very subtle change to the oscillating frequency of the VCO (it is a voltage controlled oscillator after all), or you are affecting the feedback loop of the PLL (bandwidth and gain). This can alter the output frequency such that you either make the downstream sampling margin better or worse. The effects of PLL voltage manipulation will vary from platform to platform depending upon the implementation and perhaps even temperature drift of the oscillator (insight to why things change when you go cold).

Edited by travesty - 5/2/12 at 4:44pm
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post #5 of 5
Thread Starter 
I meant the way the clock is distributed, there has to be some way of knowing what it does to help stabilize a multiplier < 56 or > 56. That's what I'm looking for. Like why does it even need to be done or messed with at a certain point? Does a higher multiplier mean a longer reference wave and there for a hiccup occurs to where you up the PLL so that it can have an output wave that gives it a steady flow without hiccups? I'm trying to piece it together, I apologize if I am missing your point in the readings.
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