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post #21 of 114
Quote:
Originally Posted by The_Manual View Post
The first simple difference between the Intel Core 2 Duo E6600 and the Intel Xeon 3060 is that the E6600 incorporates 4MB shared Level 2 Cache (Instruction + Data) whereas the Xeon 3060 supports 4MB shared Level 3 Cache (Instruction + Data). ECC is also supported on L3 cache.

As you should be aware L2 cache and L3 cache are different in properties. Level 3 cache itself is slower and has a greater latency wait period than that of Level 2 cache. Due to this fact it is cheaper to manufacture and produce.

Level 3 Cache is often used in Xeon's as it is closer to access in regards to memory.
Processor Store Directive: Level 1 > Level 2 > Level 3 > System RAM > Disk Drive.
Level 3 is next to the system memory within this structure, and therefore can more effectively be accessed if RAM is also brought into the equation.

Second difference is in relation to the socket type (thermal/electric specification).

Core 2 Duo E6600: FC-LGA
Xeon 3060: FC-LGA6

Slightly different

Also be aware that due to this slightly improved socket the bandwidth of the Intel Xeon 3060 is higher than that of the Core 2 Duo E6600.

I will get the technical information out of my manuals when I get home. The reference manuals on the Intel site are not in-depth enough compared to my developer manuals at home.
I just want to say first that I am not trying to doubt you here and your knowlege might be great and all but one thing I have noticed with lots of products is theory, design and marketing don't always hold up to real world. It's great that you have the knowledge and can explain something here but I would like to see if you or anyone else out here has some real world exampled to compare the two cpu's at.

all I ever hear if xeon can't overclock but number cruch great e6600 overclocks great but isn't the number cruncher though it is still better at games.

then I also hear things like week 28 are good for e6600 cause they have better silicon but then again xeons have the best silicon yet still can't overclock well.

it's not you that I am trying to point all this at. if anything with you I am just trying to say the info is cool and all but to me doesn't mean much without real world examples
the rest is pointed to a lot of other people I see here giving all this information that just doesn't make any sense.



point of this thread come on guys unless you have real world data it's going to be hard for me to take most of what you say as gospel
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post #22 of 114
Granted that hypotheses and theories do not exactly come to the correct conclusion in real life, but in this case I do not have theories

What I have informed you in this thread is part of the design structure and implementation of the Core Micro-Architecture.

I myself have tested all Core 2 Duo processors (E6300-X6800). I have also had the privilege of extensive testing on Xeon class processors from the 3000 and 7000 series.

The design structure of Intel Xeon class processors is to follow the specific trend of mathematical processors for servers and workstations. Whereas Core 2 Duo (Desktop) is designed to for-fill the requirements of the average/hardcore end user.

Most theories in regards to computers can be proved with computing laws, like Amdahl's Law and Pollack's Rule.

I will comment on this in the morning, but I’m off for the night.
post #23 of 114
As far as I'm aware, The_Manual is working in the high ends of Intel, so never be in doubt about what he writes with Intel CPUs.
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post #24 of 114
Quote:
Originally Posted by The_Manual View Post
Granted that hypotheses and theories do not exactly come to the correct conclusion in real life, but in this case I do not have theories

What I have informed you in this thread is part of the design structure and implementation of the Core Micro-Architecture.

I myself have tested all Core 2 Duo processors (E6300-X6800). I have also had the privilege of extensive testing on Xeon class processors from the 3000 and 7000 series.

The design structure of Intel Xeon class processors is to follow the specific trend of mathematical processors for servers and workstations. Whereas Core 2 Duo (Desktop) is designed to for-fill the requirements of the average/hardcore end user.

Most theories in regards to computers can be proved with computing laws, like Amdahl's Law and Pollack's Rule.

I will comment on this in the morning, but I’m off for the night.
why do you have to be off in the other end of the world. it's only 4p here and I'm interested in hearing what you have to say.


but if you could post some more examples or explain some more I would be happy.
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post #25 of 114
Sorry about living in the UK, I have to admit it does get annoying when I want to talk to the US personnel on this site, as I'm usually in bed when they do manage to come online.

First off, no I do not work for Intel, I don't think they would let me join their corporation at the age of 17 somehow
However I do extensive work with their processors at the architectural level.
My main focus is on Processor Cache Systems, SIMD and Branch Prediction.

My current engineering project is in regards to the Virtual Address eXtension Architecture. The older members on this forum should know what this is, if they remember it. VAX was the best architecture in existence in my opinion. It defined the computer performance term MIPS.

Xeon's have always troubled me, why design a processor that is very similar to a desktop processor with little differences that will often not be noticeable?

So in the past I have been looking at what the Xeon itself does actually have to offer that would demonstrate a need for its original design.

Cache

The first was that Workstation and Server Applications seem to have a much higher requirement for Internal Storage (Cache/DRAM). Therefore the Xeon servers have been designed to offer a more sophisticated caching system to that of desktop units. This reduces the amount of Capacity and Conflict misses.

Obviously when increasing the cache you generate problems. Increasing the cache size on processors means that the processor will have to divert clock cycles to cache allocation to improve its performance.

Obviously you could just reduce the clock speed of these processors. You could do this because the cache runs at full speed e.g. 3 GHz processor = 3GHz cache. If you reduce the clock speed the cache will also run slower and therefore require less cycles diverted to cache allocation. However your processor will also run slower.

Unfortunately I am not a good graphics designer or else I would give you a nice diagram about Capacity Misses. As I am not I will have to explain.

Cache is made up of two separate arrays. It contains the data array and the tag array.
The Data array contains the information that will inform the computer of the size of the Internal Memory (i.e. 512KB, 4096KB etc). It also contains all the data that is being stored.
The Tag array contains all the addresses of the values that are currently stored within the data array. We could call this an index

Each part within the data array contains it own tag which is called a cache line. If a miss occurs during the FETCH procedure the entire cache line has to be replaced.

I don't think I will bore you anymore. The simple fact is you need more cache to reduce this problem, if you do not have enough the entire cache line must be replaced. This obviously takes time and wastes resources.
Xeon processors often use Level 3 cache as it is faster to transfer data between L3 and Main Memory.

Branch Prediction

Cache is involved here again. Inside both of these processors is a special type of cache called Branch Prediction Cache.
Branch prediction is simply what the name suggests. The processor simply guesses which instruction should be fetched next.
Large amounts of instructions are branches, therefore a pipeline processor would encounter issues with branched instructions. This is why we have branch prediction technologies implemented.

If we did not have branch prediction we would encounter numerous pipeline breaks. Therefore a massive latency would be detected because the entire branch must be resolved before continuing.
The branch prediction system can obviously make mistakes and incorrect instructions can be fetched. The performance penalty is less than if none had been predicted in the first place however
The lost cycles due to this problem are called Branch Mispredict Penalties.

Note: Two bit prediction is most commonly used. The cache memory stores two bit counters for each recently accessed branch. This is called The Branch Prediction History Table. You don't really need to know much about this, unless you want me to explain.

Now onto the Xeon issue, instead of giving you a rundown of Branch Prediction.

Have you heard of the SPEC (Standard Performance Evaluation Corporation)benchmarking system?
Within this benchmarking system is a benchmark to determine Prediction Accuracy.

I myself have tested this on my Core 2 Duo E6600 and a Intel Xeon 3070.

Application Used: Modified SPEC95 (x86, IA-32[e])
Test Used: 4096 Entry. 2-bit Branch Prediction Cache
Core 2 Duo E6600 Score: ~87% Accuracy
Xeon 3070 Score: ~96% Accuracy

Therefore as this test has been repeated several times and an average derived it is logical to say that the Xeon's ability to work with Branch Prediction is greater, therefore greater performance is obtained.

SIMD

Not enough room in this post to add information on SIMD
post #26 of 114
thats a good read, thanks for posting that up, interesting- so if i get this right a xeon oced is going to have a harder time to deal with the higher speeds then say a e6600 would if you were to oc that right or did i totally miss something
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post #27 of 114
so where do you come pu with all this info for a 17 year old.

any more info you care to share?

what is Virtual Address eXtension?
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post #28 of 114
This is why I love this site. This thread has taught me so much. The manual I believe is correct, however, the fact that the Xeons won't overclock as well as the core2 processors baffles me. I mean, we saw the Opteron vs. Athlon saga didn't we? And also the fact that Xeons run cooler (mentioned somewhere) means that being able to overclock would be an attribute. There aren't too many reviews on the Xeons, so I'm too sure. Does the very architecture of the chip determine overclocking ability? Or is it simply the power it dissipates?

Nrgx.
post #29 of 114
Quote:
Originally Posted by The_Manual View Post
Sorry about living in the UK, I have to admit it does get annoying when I want to talk to the US personnel on this site, as I'm usually in bed when they do manage to come online.

First off, no I do not work for Intel, I don't think they would let me join their corporation at the age of 17 somehow
However I do extensive work with their processors at the architectural level.
My main focus is on Processor Cache Systems, SIMD and Branch Prediction.

My current engineering project is in regards to the Virtual Address eXtension Architecture. The older members on this forum should know what this is, if they remember it. VAX was the best architecture in existence in my opinion. It defined the computer performance term MIPS.

Xeon's have always troubled me, why design a processor that is very similar to a desktop processor with little differences that will often not be noticeable?

So in the past I have been looking at what the Xeon itself does actually have to offer that would demonstrate a need for its original design.

Cache

The first was that Workstation and Server Applications seem to have a much higher requirement for Internal Storage (Cache/DRAM). Therefore the Xeon servers have been designed to offer a more sophisticated caching system to that of desktop units. This reduces the amount of Capacity and Conflict misses.

Obviously when increasing the cache you generate problems. Increasing the cache size on processors means that the processor will have to divert clock cycles to cache allocation to improve its performance.

Obviously you could just reduce the clock speed of these processors. You could do this because the cache runs at full speed e.g. 3 GHz processor = 3GHz cache. If you reduce the clock speed the cache will also run slower and therefore require less cycles diverted to cache allocation. However your processor will also run slower.

Unfortunately I am not a good graphics designer or else I would give you a nice diagram about Capacity Misses. As I am not I will have to explain.

Cache is made up of two separate arrays. It contains the data array and the tag array.
The Data array contains the information that will inform the computer of the size of the Internal Memory (i.e. 512KB, 4096KB etc). It also contains all the data that is being stored.
The Tag array contains all the addresses of the values that are currently stored within the data array. We could call this an index

Each part within the data array contains it own tag which is called a cache line. If a miss occurs during the FETCH procedure the entire cache line has to be replaced.

I don't think I will bore you anymore. The simple fact is you need more cache to reduce this problem, if you do not have enough the entire cache line must be replaced. This obviously takes time and wastes resources.
Xeon processors often use Level 3 cache as it is faster to transfer data between L3 and Main Memory.

Branch Prediction

Cache is involved here again. Inside both of these processors is a special type of cache called Branch Prediction Cache.
Branch prediction is simply what the name suggests. The processor simply guesses which instruction should be fetched next.
Large amounts of instructions are branches, therefore a pipeline processor would encounter issues with branched instructions. This is why we have branch prediction technologies implemented.

If we did not have branch prediction we would encounter numerous pipeline breaks. Therefore a massive latency would be detected because the entire branch must be resolved before continuing.
The branch prediction system can obviously make mistakes and incorrect instructions can be fetched. The performance penalty is less than if none had been predicted in the first place however
The lost cycles due to this problem are called Branch Mispredict Penalties.

Note: Two bit prediction is most commonly used. The cache memory stores two bit counters for each recently accessed branch. This is called The Branch Prediction History Table. You don't really need to know much about this, unless you want me to explain.

Now onto the Xeon issue, instead of giving you a rundown of Branch Prediction.

Have you heard of the SPEC (Standard Performance Evaluation Corporation)benchmarking system?
Within this benchmarking system is a benchmark to determine Prediction Accuracy.

I myself have tested this on my Core 2 Duo E6600 and a Intel Xeon 3070.

Application Used: Modified SPEC95 (x86, IA-32[e])
Test Used: 4096 Entry. 2-bit Branch Prediction Cache
Core 2 Duo E6600 Score: ~87% Accuracy
Xeon 3070 Score: ~96% Accuracy

Therefore as this test has been repeated several times and an average derived it is logical to say that the Xeon's ability to work with Branch Prediction is greater, therefore greater performance is obtained.

SIMD

Not enough room in this post to add information on SIMD
ok this is way over my head now haha
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post #30 of 114
Most of the information that I have learnt has come from self study, with small parts tying in with my school work, mainly the physics and mathematics parts.
I used to own several computer architect books. These are what mostly boosted my knowledge substantially, almost enough to quote exact phrases from the books themselves.
I still own all my Intel Architecture 32/32e and Intel Architecture 64 manuals. These I do often look at to make sure that I still remember all of the data contained within, as it is rather detailed (far more than the reference manuals).

Virtual Address Extension (VAX) is a computer architecture designed by DEC in the mid 1970's. This architecture is far more sophisticated than x86.

DEC launched the VAX-11/780 computer in 1987. It was marketed to the public as a 1MIPS computer. It was able to accomplish 1 Million Instructions Per Second (MIPS) and was therefore marketed as such (obviously).
However after extensive testing it was actually determined that the actual rate of instruction was 0.5MIPS.
VAX was able to accomplish 100% additional processing within its core and therefore its performance equated to 1MIPS.
It was capable of accomplishing a work load with fewer instructions due to its onboard "Complicated Instructions".

Virtual Address eXtension is the only architecture that is capable of direct Memory > Memory Computation Instructions. All other architectures can only accomplish Memory > Register (and vice versa). Which is why I took an interest in it
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