Originally Posted by icehotshot
This is false. They don't have high leakage, the transistors are just very densely packed. As they go smaller it will continue to be more difficult to remove the heat, so even though they produce less heat than the previous generation, they will potentially have higher temperatures.
Here is a quote from INTEL.
Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage
Here is a quote from the hardwarecanucks review.
It’s pretty clear to us that Intel is using very low leakage transistors with IVB, and when you combine extremely high transistor density with a die that has half the surface area of Sandy Bridge, the temperature situation gets out of control quickly when overvolting.
With that said, having a better TIM like Liquid Pro should help decrease temperatures quite a bit because of the better heat transfer, which IB is having a hard time with at the moment because the transistors are so densely packed and there isn't a whole lot of area for the heat dissipation.
First, Intel's DESIGN
enables the chips to operate at lower voltages with lower leakage. If they fab process is flawed in some way right now then obviously the chip is not going to be "as designed".
Second, the reviewers own words show he has no idea what he's talking about and just repeating things he's heard, specifically "with a die that has half the surface area of Sandy Bridge". A)Going from 32nm to 22nm it is physically impossible
to reduce the die area by half (22nm is NOT
50% smaller than 32nm). B)Actual measurements of dies: Sandy Bridge I7-2960xm = 10.54mm by 21.88mm = 230.61mm squared, Ivy Bridge Mobile Quad Core: 8.52×20.26= 172.6152.
That's about a 20 - 25% decrease in die size. Not enough to explain the massive temperature spikes during OC. I just don't buy the argument that "increased chip density creates more heat and reduced die = can't get rid of the heat" It ignores several things namely that as you decrease size you normally decrease power consumed. Quote -
"- As lithography moves to smaller size ( 45 nm to 32 nm), you can pack up more number of dies in a given wafer. The cost of production per die reduces.
- As you increase the transistor count, the die size grows, the cost to produce increases, failure rate increases but the performance, generally increases.
- As lithography moves to smaller size, the Transistor delay reduces and the maximum frequency at which the processor can operate increases.
- As lithography moves to smaller size, the voltage at which the gate can reduces and the power requirement reduces."
In the case of Ivy Bridge the Voltage is supposed to REALLY be reduced so that even with the higher current draw it's offset and consumes less power (and thereby generates less heat) than SB. Also by that kind of logic we should have seen the same type of temperature increases as the fabs have moved from 90nm to 65nm, 65nm to 45nm and 45nm to 32nm. What we saw instead were chips that we more effecient and consumed less power (at the same speed) than their predecessors. So if it's not the TIM, and it's not the "die shrink" than that leaves only one possibility (which explains why IB V's aren't 30% or more lower than SB) that Fabrication problems are causing high leakage within the chip.