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[Video Added + Watercooling Results] Replacing the internal IHS TIM of an i7 3770K - Page 12

post #111 of 298
Quote:
Originally Posted by Cyclops View Post

Not exactly. The metal in the heatsink have to travel a long way till it go the heatsink blades, as water absorbs it and displaces it almost instantly.

As I note here, the heat capacity of water is such that it's far better at cooling even with the extra thermal interface. You can only do so much with forced convection.
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post #112 of 298
Thread Starter 
Quote:
Originally Posted by SeanPoe View Post

@Cyclops: Do you still plan to try a test without the IHS?

Yes, I'll get off work in about 4 hours and see what I can do. I need to remove the retention arm, probably. Im also planing on doing a small loop using a Raystorm block with and without the IHS to see the difference.
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post #113 of 298
Quote:
Originally Posted by Cyclops View Post

Yes, I'll get off work in about 4 hours and see what I can do. I need to remove the retention arm, probably. Im also planing on doing a small loop using a Raystorm block with and without the IHS to see the difference.

You have to remove the two torx screws @ the back..You can leave the front one and slide the bracket out.Be careful and take your time..Don't smash it down too hard..snug is good.
 
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post #114 of 298
Quote:
Originally Posted by icehotshot View Post

proof.gif
This is false. They don't have high leakage, the transistors are just very densely packed. As they go smaller it will continue to be more difficult to remove the heat, so even though they produce less heat than the previous generation, they will potentially have higher temperatures.
Here is a quote from INTEL.
Quote:
Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage
source
Here is a quote from the hardwarecanucks review.
Quote:
It’s pretty clear to us that Intel is using very low leakage transistors with IVB, and when you combine extremely high transistor density with a die that has half the surface area of Sandy Bridge, the temperature situation gets out of control quickly when overvolting.
source
With that said, having a better TIM like Liquid Pro should help decrease temperatures quite a bit because of the better heat transfer, which IB is having a hard time with at the moment because the transistors are so densely packed and there isn't a whole lot of area for the heat dissipation.

First, Intel's DESIGN enables the chips to operate at lower voltages with lower leakage. If they fab process is flawed in some way right now then obviously the chip is not going to be "as designed".

Second, the reviewers own words show he has no idea what he's talking about and just repeating things he's heard, specifically "with a die that has half the surface area of Sandy Bridge". A)Going from 32nm to 22nm it is physically impossible to reduce the die area by half (22nm is NOT 50% smaller than 32nm). B)Actual measurements of dies: Sandy Bridge I7-2960xm = 10.54mm by 21.88mm = 230.61mm squared, Ivy Bridge Mobile Quad Core: 8.52×20.26= 172.6152.
400

That's about a 20 - 25% decrease in die size. Not enough to explain the massive temperature spikes during OC. I just don't buy the argument that "increased chip density creates more heat and reduced die = can't get rid of the heat" It ignores several things namely that as you decrease size you normally decrease power consumed. Quote -
"- As lithography moves to smaller size ( 45 nm to 32 nm), you can pack up more number of dies in a given wafer. The cost of production per die reduces.

- As you increase the transistor count, the die size grows, the cost to produce increases, failure rate increases but the performance, generally increases.

- As lithography moves to smaller size, the Transistor delay reduces and the maximum frequency at which the processor can operate increases.

- As lithography moves to smaller size, the voltage at which the gate can reduces and the power requirement reduces."

In the case of Ivy Bridge the Voltage is supposed to REALLY be reduced so that even with the higher current draw it's offset and consumes less power (and thereby generates less heat) than SB. Also by that kind of logic we should have seen the same type of temperature increases as the fabs have moved from 90nm to 65nm, 65nm to 45nm and 45nm to 32nm. What we saw instead were chips that we more effecient and consumed less power (at the same speed) than their predecessors. So if it's not the TIM, and it's not the "die shrink" than that leaves only one possibility (which explains why IB V's aren't 30% or more lower than SB) that Fabrication problems are causing high leakage within the chip.
post #115 of 298
Cyclops,

Have you looked at the paste and how thick it is between the IHS and the die? It should be VERY VERY minimal! If you refer to my nvidia IHS guide, you sand the edges of the IHS down to make the primary area of contact on the IHS to be the die.
450

Notice how little paste is there between the die and IHS.
450

Might want to take it out again and inspect it.

IF the IHS's primary contact to the CPU is by means of the edges around the die, you'll get even lower temps by when you sand down the IHS edges. It's quite easy, set the IHS on a glass surface with some 800-1000grit sandpaper and just sand it down, the inner area that makes contact with the die is recessed so you'll only be sanding the edges of the IHS that possibly make contact first before the die does...

Might look into that! thumb.gif
post #116 of 298
Quote:
Originally Posted by BinaryDemon View Post

'Of course' the temps are going to drop if you use a better quality TIM, but it seems that even the best options aren't dropping the temps enough to make overclocking Ivy Bridge comparable to Sandy Bridge clock speeds.
But since clock for clock the IB is faster, you get greater advantage every bit you can overclock an IB than the SB gains.
Quote:
Originally Posted by BinaryDemon View Post

Intel probably opted for a cost-savings TIM after their internal testing showed it wasnt a significant factor for higher overclocks.
Since you were wrong on your prior point, this logic doesn't follow. Anyway, the logic is flawed. So your hypothesis is that Intel wants to allow "high overclocks" and since those arent obtainable it would hamstring the CPU with poor cooling thereby constraining all overclocks? That makes no sense. That's like Chevrolet realizing it can't build a car faster than the latest Ferrari so it gives up building cars entirely.
post #117 of 298
Quote:
Originally Posted by Cakewalk_S View Post

Cyclops,
Have you looked at the paste and how thick it is between the IHS and the die? It should be VERY VERY minimal! If you refer to my nvidia IHS guide, you sand the edges of the IHS down to make the primary area of contact on the IHS to be the die.

Notice how little paste is there between the die and IHS.

Might want to take it out again and inspect it.
IF the IHS's primary contact to the CPU is by means of the edges around the die, you'll get even lower temps by when you sand down the IHS edges. It's quite easy, set the IHS on a glass surface with some 800-1000grit sandpaper and just sand it down, the inner area that makes contact with the die is recessed so you'll only be sanding the edges of the IHS that possibly make contact first before the die does...
Might look into that! thumb.gif

Woohoo! wheee.gif This is good stuff! :yessir.gif: thumbsupsmiley.png
Edited by Schmuckley - 5/13/12 at 11:15am
 
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post #118 of 298
Thread Starter 
Quote:
Originally Posted by Cakewalk_S View Post

Cyclops,
Have you looked at the paste and how thick it is between the IHS and the die? It should be VERY VERY minimal! If you refer to my nvidia IHS guide, you sand the edges of the IHS down to make the primary area of contact on the IHS to be the die.
Might want to take it out again and inspect it.
IF the IHS's primary contact to the CPU is by means of the edges around the die, you'll get even lower temps by when you sand down the IHS edges. It's quite easy, set the IHS on a glass surface with some 800-1000grit sandpaper and just sand it down, the inner area that makes contact with the die is recessed so you'll only be sanding the edges of the IHS that possibly make contact first before the die does...
Might look into that! thumb.gif

I'll look into that when I get home tonight. I made sure that I used just enough TIM and I spread it as evenly as I could.

As for the original paste, it was completely dry when I removed the IHS. I don't know what that says about the quality of the tim but whenever I use AS-5 or MX-4, the grease is always "greasy" as in it's in a semi-liquid form that you can wipe with a tissue without it disintegrating like it did with the original paste.
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post #119 of 298
Quote:
Originally Posted by SeanPoe View Post

5ghz for a IB is like 5400mhz for a SB. SB at 5400 on air is unheard of. So it's still a great overclock.
SB isn't built using 22nm tech, not to mention it came out over a year before IB did...
post #120 of 298
Also, FYI, you want the thinnest/least viscus thermal paste for direct die/IHS/Lapped surfaces. Thick pastes like this ceramique grease I've got HATES to spread when applied to a perfectly lapped surface. It just can't spread well. So hopefully that MX4 is a very thin runny grease. I got mx2 and that stuff worked amazing! Yea! Def look at the areas of contact with the IHS. I'd highly check into sanding down the edges of the IHS. you could easily get another 5C drop if the contact is being made on the sides of the die and not the actual die itsself.


Get pics! Hope it works well for ya!
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