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[TPU] TIM is Behind Ivy Bridge Temperatures After All - Page 14

post #131 of 288
Quote:
Originally Posted by Domino View Post

You guys must really like infractions since you go off-topic on the most pointless of things.
Anyways, the heat issues is more due to the small surface area of chip itself. And as blameless has said, the performance differences is far too great.

Oh lord....another "die shrink" theorist.
post #132 of 288
Quote:
Originally Posted by Bubba Hotepp View Post

Oh lord....another "die shrink" theorist.

Given equal transistor count, operating power + leakage and identical design, temperatures would be higher in a smaller chip.
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post #133 of 288
i wish amd would find a uber cooling medium .cause if they did intel would be in a bind.i like a bit of competition
post #134 of 288
Quote:
Originally Posted by Homeles View Post

Given equal transistor count, operating power + leakage and identical design, temperatures would be higher in a smaller chip.

Only problem is....it's NOT an identical design. Sandy Bridge = planar transistors, Ivy Bridge = tri-gate transistors. Since you haven't been reading the whole thread I'll summarize. Tri-gate transistors draw higher current (electron flow) than planar designs. The reasons why are well documented in any article that does an in depth explanation of tri-gate transistor technology so I'll skip that for now. The advantage of tri-gate is that not only in the "off" phase does it use almost no power at all (close to zero), but it requires less voltage (potential) to operate properly. Once again I'll post the formula, watts (derived unit of power) = voltage (potential for electron flow between two points or alternatively called "electrical tension") multiplied by current (flow of electrons, or in electrolytes ions, or both in plasma). Or simply W = V x I (or A for amps but conventionally shown as I). With two CPU'S that have DIFFERENT levels of current flow, Chip A being MORE than Chip B, in order for them to have the SAME Power usage (W) then voltage MUST be LOWER. It's non negotiable, it's a LAW of physics and electricity.

Quote "In terms of electromagnetism, one watt is the rate at which work is done when one ampere (A) of current flows through an electrical potential difference of one volt (V). W = V * A"
http://en.wikipedia.org/wiki/Watt

All it takes is a look around the forums to see that people are reporting HUGELY varying levels of required voltages at different OC levels WITH higher temps being reported for higher voltages and lower temps reported for the few lucky to get chips that operate as designed at lower voltages. (read one or two pages back in this thread for a prime example). THAT is theoretically, physically, and logically IMPOSSIBLE if the "heat problems" were due to the 20% reduction in die surface area. ALL of the chips would be running hot AND using the same basic range of voltages that would be within a few percentage points of each other with a few "bad" chips thrown in as usual that have high leakage. Instead we're seeing the opposite, a high percentage of the chips are exhibiting signs of high leakage (evidenced by higher than normal voltages for the design accompanied by high temperatures).

I can tell you exactly what happened. It's obvious. They are having fabrication problems (as evidenced by the delays), probably too many impurities and because of the new "atom layer by atom" layer process their using they haven't figured out how to minimize it. Remember a small amount of impurities is the difference between a $1000 dollar CPU and a bargain basement throw away chip. Someone made an executive decision because of intense pressure. With already being behind schedule, AMD's pending release of Piledriver, and an undetermined amount of time to "fix" the problem, some executive decided to release as is and fix it with new revisions (steppings). A "get it out there and we'll fix it later" approach. Doesn't take a genius to see what's happening. The question will be how much backlash intel will face over this debacle.
post #135 of 288
Okay so getting back to the topic, it sounds like there are several issues with Ivy Bridge that could lead to the chip running hotter. That still doesn't explain why then they would choose to use such a cheap thermal paste, if they knew the chip runs hot shouldn't they have improved the heat transfer?


Is it clear why they moved away from solder in the first place? Was there another inherit issue with solder that made thermal paste the better option? (Besides possible savings in cost).
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post #136 of 288
Quote:
Originally Posted by Italianguy View Post

Okay so getting back to the topic, it sounds like there are several issues with Ivy Bridge that could lead to the chip running hotter. That still doesn't explain why then they would choose to use such a cheap thermal paste, if they knew the chip runs hot shouldn't they have improved the heat transfer?
Is it clear why they moved away from solder in the first place? Was there another inherit issue with solder that made thermal paste the better option? (Besides possible savings in cost).

Easy, they needed to get the chips out fast because of the delay, and since they're going to run hot anyways throw some TIM on there and cut costs and time to get it to market. I'll bet money that on the next stepping not only are they running at lower voltages with lower temperatures but will have a soldered IHS.
post #137 of 288
Quote:
Originally Posted by Bubba Hotepp 
All it takes is a look around the forums to see that people are reporting HUGELY varying levels of required voltages at different OC levels WITH higher temps being reported for higher voltages and lower temps reported for the few lucky to get chips that operate as designed at lower voltages. (read one or two pages back in this thread for a prime example). THAT is theoretically, physically, and logically IMPOSSIBLE if the "heat problems" were due to the 20% reduction in die surface area. ALL of the chips would be running hot AND using the same basic range of voltages that would be within a few percentage points of each other with a few "bad" chips thrown in as usual that have high leakage. Instead we're seeing the opposite, a high percentage of the chips are exhibiting signs of high leakage (evidenced by higher than normal voltages for the design accompanied by high temperatures).

Your assertion about the impossibility of lost die area having an impact is totally incorrect, and your own explanation is a direct counter to it. The hotter running Ivy chips are hotter running because they produce more heat relative to their surface area than the cooler running ones, because of the factors you just mentioned.

If heat flux increases, temperature increases, assuming a system with similar thermal conductivity.

Relative to older chip, Ivy generally lost more surface area than it lost in heat production. The CPU cores are only a bit over half (I say half because the IGP is completely idle in the vast majority of tests and a large portion of Ivy is IGP; the cores themselves have very similar transistor counts and a 22nm transistor takes very roughly half the area of a 32nm one) the size of Sandy's, yet (at load) they require upwards of 3/4ths of the power and make upwards of 3/4ths the heat. Even if everything else (same transistor design, same IHS TIM, etc) was identical, this difference in heatflux could explain a significant portion of the temperature differences seen.

Obviously, with Ivy, there are other factors, and the inferior IHS TIM is almost certainly one of them, but it's not the only factor.
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post #138 of 288
Quote:
Originally Posted by Blameless View Post

Quote:
Originally Posted by Bubba Hotepp 
All it takes is a look around the forums to see that people are reporting HUGELY varying levels of required voltages at different OC levels WITH higher temps being reported for higher voltages and lower temps reported for the few lucky to get chips that operate as designed at lower voltages. (read one or two pages back in this thread for a prime example). THAT is theoretically, physically, and logically IMPOSSIBLE if the "heat problems" were due to the 20% reduction in die surface area. ALL of the chips would be running hot AND using the same basic range of voltages that would be within a few percentage points of each other with a few "bad" chips thrown in as usual that have high leakage. Instead we're seeing the opposite, a high percentage of the chips are exhibiting signs of high leakage (evidenced by higher than normal voltages for the design accompanied by high temperatures).
Your assertion about the impossibility of lost die area having an impact is totally incorrect, and your own explanation is a direct counter to it. The hotter running Ivy chips are hotter running because they produce more heat relative to their surface area than the cooler running ones, because of the factors you just mentioned.
If heat flux increases, temperature increases, assuming a system with similar thermal conductivity.
Relative to older chip, Ivy generally lost more surface area than it lost in heat production. The CPU cores are only a bit over half (I say half because the IGP is completely idle in the vast majority of tests and a large portion of Ivy is IGP; the cores themselves have very similar transistor counts and a 22nm transistor takes very roughly half the area of a 32nm one) the size of Sandy's, yet (at load) they require upwards of 3/4ths of the power and make upwards of 3/4ths the heat. Even if everything else (same transistor design, same IHS TIM, etc) was identical, this difference in heatflux could explain a significant portion of the temperature differences seen.
Obviously, with Ivy, there are other factors, and the inferior IHS TIM is almost certainly one of them, but it's not the only factor.

Let's take your claims one by one.

First I never said the die shrink has zero impact. I said it's impossible that it is the cause of the massive heat spikes seen while overclocking. Having an affect and 'being the cause of" are two totally different things. The entire reason intel switched to the tri-gate design is because it requires significantly less voltage to operate. Even with the increased current it would still by design draw less power and produce less heat than the previous design.

Secondly, let's examine your claim that Ivy Bridge is currently operating at "3/4 the power and makes upwards of 3/4 the heat". Here are two lists of overclocked SB and IB chips
http://www.overclock.net/t/968053/official-the-sandy-stable-club-guides-voltages-temps-bios-templates-inc-spreadsheet/0_20
http://www.overclock.net/t/1247869/ivy-bridge-stable-suicide-club-guides-voltages-temps-bios-templates-inc-spreadsheet/300_20

We'll take the first 15 Sandy Bridges in the list that are clocked at 4.5GHz. We see a range of voltages of 1.260V to 1.404V with the bulk of the results in the 1.32-1.34 range. That's a disparity of .144V. Reported Temperatures range from 67-73-73-73 for the 1.404 result to 64-68-67-69 for the 1.260 result.

Now let's look at the posted results for Ivy Brige so far. 6 results clocked at 4.5GHz. We see a range of 1.176V - 1.320V for 5 of them and only ONE a voltage of 1.092V. That's a disparity of 0.228V. We also see a range of temperatures of 84-90-87-84 for 1.32V to 75-79-81-77 for the 1.176V result. Only the 1.092V result is posting similar temperatures to SB with 62-70-68-64 WHICH IS EXACTLY HOW IT SHOULD BE. When current is HIGHER, Voltage MUST BE LOWER for the power consumption and heat dissapation to remain the same. If this is a "die shrink" issue then please explain to me how the sole low result is even ABLE to exist?? It would have the SAME heat dissipation problems as the other results. It's simple. Ivy Bridge operates with significantly higher current on the gates yet as we can see, with ONE exception, the voltages are not much lower than Sandy Bridge clock for clock and yet everyone STILL parrots the same party line that it's the TIM, or it's the die shrink.

YES TIM instead of solder is playing a role, YES die shrink is playing a role, albeit small ones. They DO NOT however explain the rest of the evidence.
Edited by Bubba Hotepp - 5/15/12 at 2:24am
post #139 of 288
Quote:
Originally Posted by Bubba Hotepp View Post

I said it's impossible that it is the cause of the massive heat spikes seen while overclocking.

Which is the same thing as saying that heat flux doesn't matter, when it does.
Quote:
Originally Posted by Bubba Hotepp View Post

Even with the increased current it would still by design draw less power and produce less heat than the previous design.

Yes, but the reduction in power is no where near as large as the reduction in area.
Quote:
Originally Posted by Bubba Hotepp View Post

Secondly, let's examine your claim that Ivy Bridge is currently operating at "3/4 the power and makes upwards of 3/4 the heat". Here are two lists of overclocked SB and IB chips
http://www.overclock.net/t/968053/official-the-sandy-stable-club-guides-voltages-temps-bios-templates-inc-spreadsheet/0_20
http://www.overclock.net/t/1247869/ivy-bridge-stable-suicide-club-guides-voltages-temps-bios-templates-inc-spreadsheet/300_20
We'll take the first 15 Sandy Bridges in the list that are clocked at 4.5GHz. We see a range of voltages of 1.260V to 1.404V with the bulk of the results in the 1.32-1.34 range. That's a disparity of .144V. Reported Temperatures range from 67-73-73-73 for the 1.404 result to 64-68-67-69 for the 1.260 result.
Now let's look at the posted results for Ivy Brige so far. 6 results clocked at 4.5GHz. We see a range of 1.176V - 1.320V for 5 of them and only ONE a voltage of 1.092V. That's a disparity of 0.228V. We also see a range of temperatures of 84-90-87-84 for 1.32V to 75-79-81-77 for the 1.176V result. Only the 1.092V result is posting similar temperatures to SB with 62-70-68-64 WHICH IS EXACTLY HOW IT SHOULD BE. When current is HIGHER, Voltage MUST BE LOWER for the power consumption and heat dissapation to remain the same.

No arguments here, though that low voltage sample doesn't imply higher current, unless power consumption was the same as SB, and that is not typical.
Quote:
Originally Posted by Bubba Hotepp View Post

If this is a "die shrink" issue then please explain to me how the sole low result is even ABLE to exist?? It would have the SAME heat dissipation problems as the other results.

Leakage, current draw, and thus power consumption and heat dissipation can vary considerably from chip to chip, even at similar voltages and clock speeds. It stands to reason that the "sole low result" you mention is a lower leakage example, or a fluke.
Quote:
Originally Posted by Bubba Hotepp View Post

It's simple. Ivy Bridge operates with significantly higher current on the gates yet as we can see, with ONE exception, the voltages are not much lower than Sandy Bridge clock for clock and yet everyone STILL parrots the same party line that it's the TIM, or it's the die shrink.

Ivy typically doesn't draw more current than Sandy, as power consumption tests have shown. If it did, it would imply heat density was even higher, and that the die shrink was even more relevant.
Quote:
Originally Posted by Bubba Hotepp View Post

YES TIM instead of solder is playing a role, YES die shrink is playing a role, albeit small ones. They DO NOT however explain the rest of the evidence.

There is no "rest of the evidence". With the same cooler and ambients a CPU runs hotter or colder because of differences in it's heat flux, and the thermal conductivity of it's packaging.

Simple math shows that core die area has typically decreased much more than power consumption, this means a higher heat flux, which in turn means higher temperatures at the same thermal resistance (and because of the change of TIM, thermal resistance actually got worse).
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post #140 of 288
Quote:
Originally Posted by Blameless View Post

There is no "rest of the evidence". With the same cooler and ambients a CPU runs hotter or colder because of differences in it's heat flux, and the thermal conductivity of it's packaging.
Simple math shows that core die area has typically decreased much more than power consumption, this means a higher heat flux, which in turn means higher temperatures at the same thermal resistance (and because of the change of TIM, thermal resistance actually got worse).

You need to go read up on basic electronic theory as well as tri-gate technology because you're confusing "Power" with "Current". They are NOT the same.

Quote directly from Intel -

•Dramatic performance gain at low operating voltage, better than Bulk, PDSOI or FDSOI 37% performance increase at low voltage >50% power reduction at constant performance
•Improved switching characteristics (On current vs. Off current)
•Higher drive current for a given transistor footprint
•Only 2-3% cost adder (vs. ~10% for FDSOI)

Source - http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf tri-gate transistor benefits slide

Note the first line "Dramatic performance gain at low operating voltage", and line 3 "Higher drive current" and now tell me the the chips released so far are functioning as designed and it's not a leakage issue caused by fabrication problems.

http://www.pcmag.com/article2/0,2817,2384909,00.asp - line 4 "50 percent reduction in power". (remember power, W = V (voltage) times I (current)
Edited by Bubba Hotepp - 5/15/12 at 10:22am
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