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AMD's Quad cores have large advantages over Kentsfield

post #1 of 148
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The article states what is said in the title, (ofcourse, not taking in consideration of the 9ops/12ops per cycle difference ), and the native AMD quad cores will vary from 2.6 to 3.0 ghz.

I didnt know that kentsfield just was two dualcores on one cpu

Source is here, clicky.
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post #2 of 148
sounds good, i bet the price tag will be better
    
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post #3 of 148
Quote:
but we have to remind you that until AMD has a product out that can be tested rigorously and compared to Intel's chips we will not be able to offer any real world comparisons, although we have to admit that on paper it does look good for AMD provided they can deliver the chips soon enough.

AMD's Quad cores have nothing right now, because they don't exist. Once they come out we will see what they can do.
post #4 of 148
Quote:
Originally Posted by Thumper
AMD's Quad cores have nothing right now, because they don't exist. Once they come out we will see what they can do.
lol i was about to flood all AMD's Quad cores thread about this. Its like comparing the future CPU with the CPU as of now, its pointless to compare really
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post #5 of 148
They range from 2.6-3.0Ghz quads. Still seems to low to me. I think AMD made need to get out of this architure and go for 12 or even 16 ops/cycle.
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post #6 of 148
We have to wait till there released to see how good they compare to intels Kentsfield.
post #7 of 148
Kentsfeild will choke under its own power. By using the FSB, Intel have pretty much killed it. Under full load on ALL cores, the FSB will be saturated and performance will diminish rapidly.
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post #8 of 148
Not to mention we are talking about a DUAL CHIP solution. Completely disregarding the fact that their quad core solution is likely going to come out months after Kentsfield, I don't think Intel (or myself) was too keen on using multiple chips to increase performance (excluding Tigerton and other server solutions).

I thought this was an interesting post I found on XS, explaining the possible issues with AMDs design. Interesting....

Quote:
Originally Posted by freecableguy
*Ahem.* Hate to break up this party but I must...

AMD CPUs communicates with the SPP via an HyperTransport tunnel, same as the SPP communicates with the MCP (via an HT tunnel). Placing 2 (dual-core or otherwise) dies on a single package without changing the number of CPU package pins means more than just 4 cores in one package. It also means that each die can only receive 1/2 of the maximum BW available from the PCI-e buses attached to the SPP or MCP. Same number of pins, same bus speed, same data availability....one HT link.

If you thought Intel's "antiquated" FSB design was BW limited wait until you see this. Intel knew what they were doing. They knew all they had to do was scale the FSB to get more BW. AMD has to "overclock" the IMC (or design a new one) in order to increase BW. As you can see, each design has its pros and cons. AMD is about to experience the con.

Plus don't forget, the second CPU is going to be attached via an HT link to the first CPU (the SPP only allows for one HT link via the only set of pins available). This means that all the data throughput from the second CPU (and it's associated memory) as well as any video data must pass through the first CPU on their way to the PCI/PCI-e bus. *choke*
    
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post #9 of 148
Hmm I see what he is saying, all data must pass thro the first cpu I think AMD will be able to make it so it doesnt have to pass thro the 1st cpu to be executed. Also isnt this just the same with Kentsfield, as it has an FSB bottleneck which they had to overclock to get C2D/C2Q to work (266MHz from 200MHz)?
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post #10 of 148
Quote:
Originally Posted by Mikey122687
lol i was about to flood all AMD's Quad cores thread about this. Its like comparing the future CPU with the CPU as of now, its pointless to compare really
Just on a side note, for how many months before release was C2D compared to whatever AMD had
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