Cascading TECs

So lastnight, Mindchi|l had a little free time in between punching out blocks and chillers for people. We cascaded two chillers and one single direct die. What was found out, was besides hitting -11°C or so on the cold side of the DDB(Direct Die Block), he also managed to drop the thermal resistance of the block further. Whether or not this was due to the new inlet design on the DDB (which is fully possible) or it's because chilling a TEC increases efficiency remains to be seen and is going to be tested further.

We weren't able to measure any duty cycles because the firmware was changed to allow for full temperature control which didn't have Duty Cycle on the display. Water Temps in the picture were 34.4°C and the entire cooling assembly was barely even on, probably attributed to the 77W processor. The major draw back to the entire experiment was that the Quad rad was by itself in just push configuration having to move WasteHeat(423W) + CPU(77W) = 493W, which is quite alot for a single QuadRad. I think we're short about 2 triple rads if we were following the rule of thumb. If we were able to keep the water at about 26 or 27°C, we could have knocked off 8 more degrees from the Core temps.

Ivy Bridge 3570K @ Stock, Loaded, 37°C Water (Top Controller = Direct Die [Full Power], Bottom Controller = Chillers [Set to 15°C])


Something we've noticed about distilled water, between 0 - 10°C the efficiency of the chillers drops due to the water wanting to change phase. Due to time constraints we weren't able to make a mix for the coolant to prevent that from happening so we had to limit the chillers to around 15°C

As we can see the the DDB went as low as -11°C with very little load on full power. That puts us at about 48°C dt from the hot water temps.

Ivy Bridge 3570K @ Stock, Idle, 34.4°C Water


In the pictures above, we were able to see that at approx 50% duty cycle (due to the color changing LEDs and the temperature match on the display), we were able to achieve a delta of about 34.4°C which is pretty substantial. It would take the Single DDB about 19V (~400W) to do the same. I don't wanna use hocus-pocus math, but 50% duty cycle of 3x141W, would be much less than that. Nearly half as much power used.

Ivy Bridge 3570K @ 4.8GHz, Loaded, 38.2°C Water


For the moment, this testing is on pause, as there are too many inconsistencies and there wasn't enough time to test to the fullest. We're going to let you draw your own conclusions on how efficient this will be, but we feel this is plausible; we need to just dive deeper, and at the moment there just isn't time. This was more just a proof of concept.

We will definitely come back to this!
Edited by Krow - 6/26/12 at 7:46am

Sorry, that was just for the max delta. This thing proved to be less effective in the end, but used less power than a single TEC to do achieve the same result. Kind of an obvious result, however, we also couldn't give it a good test, so it's unfair to say that it won't work. We just need to be able to devote a day or two to the testing.

One problem is the chillers were stuck at 15°C because any lower and they lost efficiency. Another was that the quad radiator couldn't cut it so we probably need another one. Another major problem is that the CPU sensors in the die are very inaccurate with the temperature range they have to deal with. According to the 3570K that was used for testing, it's stock °c/w is 0.564935 which would give it a delta of 43.5°C. However at 4.8GHz, the same °C/W would put it at a delta of 90°C at 161W, which it definitely was not. According to the CPU, the Thermal Resistance of the CPU went down to 0.374223°C/W. So something isn't right.

We'll either have to figure that out. It will be nice to just start from square one with this testing and define our constants.
Edited by Krow - 6/25/12 at 6:50pm