Quote:
Originally Posted by Conners 
Just as a reference here is my bios template on 4.1GHz I tested about 3 years ago. I doubt it will help you but might give you and Ideal of what to try... Warning: Spoiler!MB Intelligent Tweaker(M.I.T.) (Click to show)
Here's some useful info relating to reference volt settings
(edited from several PMs with Lsdme)
All reference voltages must be set with their respective "Controlling" Voltages at stock.
=============================================
CPU Termination (Vtt) Automatically changes the following if manually set >>>
CPU Reference Voltage (63% of Default Vtt/1.20) .76 ET
CPU Reference2 Voltage (67% of Default Vtt/1.20) .80 ET
MCH Reference Voltage (63% of Default Vtt/1.20) .76 ET
=============================================
DRAM Voltage Automatically changes the following if manually set >>>
MCH/DRAM Reference Voltage (50% of Default Dram Voltage)
DRAM Termination Voltage (50% of Default Dram Voltage)
Channel A Reference Voltage (50% of Default Dram Voltage)
Channel B Reference Voltage (50% of Default Dram Voltage)
==============================================
For example if you want to try 1.28 Vtt with .74 MCH Ref you must set Vtt to 1.20 first,
then go set MCH Ref to .74. Then go raise Vtt back to 1.28 and the MCH Ref will self adjust.
This is a table I created to bring some order to this madness:
Relationship of the Bios/ET6 values as a percentage of VTT (Cpu Termination) at 1.20 volts.
% of 1.20 values [before auto-adjustment]
55% = 0.660 || 60% = 0.720 || 65% = 0.780 || 70% = 0.840
56% = 0.672 || 61% = 0.732 || 66% = 0.792 || 71% = 0.852
57% = 0.684 || 62% = 0.744 || 67% = 0.804 || 72% = 0.864
58% = 0.696 || 63% = 0.756 || 68% = 0.816 || 73% = 0.876
59% = 0.708 || 64% = 0.768 || 69% = 0.828 || 74% = 0.888
Just as a reference here is my bios template on 4.1GHz I tested about 3 years ago. I doubt it will help you but might give you and Ideal of what to try... Warning: Spoiler!MB Intelligent Tweaker(M.I.T.) (Click to show)
Robust Graphics Booster ...............: Fast
CPU Clock Ratio ..........................: 8
Fine CPU Clock Ratio.....................: 0.5
CPU Frequency ...........................: 4.25 MHz
Clock Chip Control
Standard Clock Control
CPU Host Clock Control..................: [Enabled]
CPU Host Frequency (Mhz) ............: 500 Mhz
PCI Express Frequency (Mhz) .........: 100
C.I.A.2 .................................:[Disabled]
Advanced Clock Control [Press Enter]
CPU Clock Drive...........................: 800mV
PCI Express Clock Drive.................: 700mV
CPU Clock Skew (ps)....................: 0ps
MCH Clock Skew (ps)...................: 50ps
DRAM Performance Control
Performance Enhance...................: [STANDARD]
Extreme Memory Profile (X.M.P.).....: Disabled
(G)MCH Frequency Latch...............: [Auto]
System Memory Multiplier ..............: 2.00D
Memory Frequency (Mhz) ..............: 1000
DRAM Timing Selectable ................: [Manual]
Standard Timing Control
CAS Latency Time........................ 5
tRCD ......................................... 5
tRP'........................................... 5
tRAS.......................................... 15
Advanced Timing Control
tRRD........................................... 4
tWTR.......................................... 4
tWR............................................ 8
tRFC........................................... 52
tRTP........................................... 4
Command Rate (CMD) ....................: 2
Driving Strength Profiles
Driving Strength ............................: Auto
Channel A
Static tRead Value.........................: 9
tRD Phase0 Adjustment...................:Auto
tRD Phase1 Adjustment...................:Auto
tRD Phase2 Adjustment .................:Auto
tRD Phase3 Adjustment..................:Auto
Trd2rd(Different Rank)....................:Auto
Twr2wr(Different Rank)...................:Auto
Twr2rd(Different Rank)...................:Auto
Trd2wr(Same/Diff Rank)..................:Auto
Dimm1 Clock Skew Control...............:Auto ps
Dimm2 Clock Skew Control...............:Auto ps
Channel B
Static tRead Value.........................: 9
tRD Phase0 Adjustment...................:Auto
tRD Phase1 Adjustment...................:Auto
tRD Phase2 Adjustment .................:Auto
tRD Phase3 Adjustment..................:Auto
Trd2rd(Different Rank)....................:Auto
Twr2wr(Different Rank)...................:Auto
Twr2rd(Different Rank)...................:Auto
Trd2wr(Same/Diff Rank)..................:Auto
Dimm1 Clock Skew Control...............:Auto ps
Dimm2 Clock Skew Control...............:Auto ps
Motherboard Voltage Control
Voltage Type.………... Manual
CPU
CPU Vcore….……….........................: 1.38125V
CPU Termination…..... 1.200V*.......: 1.340V
CPU PLL…………………....1.500V*.......: 1.570V
CPU Referen.…………....0.755V*.......: .918V
MCH/ICH
MCH Core…………….....1.100V...........: 1.360V
MCH Reference….…….0.800V...........: .888V
MCH/DRAM Ref.…......0.900V...........: 1.050V
ICH I/O……………….....1.500V............: 1.570V
ICH Core…………...……1.100V............: 1.100V
DRAM
DRAM Voltage ……....1.800V............: 2.120V
DRAM Termination .…0.900V............: 1.050V
Channel A Reference 0.900V............: Auto
Channel B Reference 0.900V............: Auto
Advanced Settings
Limit CPUID Max. to 3.....................: [Disabled]
No-Execute Memory Protect............: [Enabled]
CPU Enhanced Halt (C1E)................: [Enabled]
C2/C2E State Support....................: [Disabled]
x C4/C4E State Support..................: [Disabled]
CPU Thermal Monitor 2(TM2) ...........: [Enabled]
CPU EIST Function.........................: [Enabled]
Virtualization Technology................: [Disabled]
Integrated Peripherals
Legacy USB Storage Detect ..............[Disabled]
I respectfully disagree with cryptedvick on reference voltages, I think they play a big part in stability. A friend of mine wrote this when I was going for 500 fsb.CPU Clock Ratio ..........................: 8
Fine CPU Clock Ratio.....................: 0.5
CPU Frequency ...........................: 4.25 MHz
Clock Chip Control
Standard Clock Control
CPU Host Clock Control..................: [Enabled]
CPU Host Frequency (Mhz) ............: 500 Mhz
PCI Express Frequency (Mhz) .........: 100
C.I.A.2 .................................:[Disabled]
Advanced Clock Control [Press Enter]
CPU Clock Drive...........................: 800mV
PCI Express Clock Drive.................: 700mV
CPU Clock Skew (ps)....................: 0ps
MCH Clock Skew (ps)...................: 50ps
DRAM Performance Control
Performance Enhance...................: [STANDARD]
Extreme Memory Profile (X.M.P.).....: Disabled
(G)MCH Frequency Latch...............: [Auto]
System Memory Multiplier ..............: 2.00D
Memory Frequency (Mhz) ..............: 1000
DRAM Timing Selectable ................: [Manual]
Standard Timing Control
CAS Latency Time........................ 5
tRCD ......................................... 5
tRP'........................................... 5
tRAS.......................................... 15
Advanced Timing Control
tRRD........................................... 4
tWTR.......................................... 4
tWR............................................ 8
tRFC........................................... 52
tRTP........................................... 4
Command Rate (CMD) ....................: 2
Driving Strength Profiles
Driving Strength ............................: Auto
Channel A
Static tRead Value.........................: 9
tRD Phase0 Adjustment...................:Auto
tRD Phase1 Adjustment...................:Auto
tRD Phase2 Adjustment .................:Auto
tRD Phase3 Adjustment..................:Auto
Trd2rd(Different Rank)....................:Auto
Twr2wr(Different Rank)...................:Auto
Twr2rd(Different Rank)...................:Auto
Trd2wr(Same/Diff Rank)..................:Auto
Dimm1 Clock Skew Control...............:Auto ps
Dimm2 Clock Skew Control...............:Auto ps
Channel B
Static tRead Value.........................: 9
tRD Phase0 Adjustment...................:Auto
tRD Phase1 Adjustment...................:Auto
tRD Phase2 Adjustment .................:Auto
tRD Phase3 Adjustment..................:Auto
Trd2rd(Different Rank)....................:Auto
Twr2wr(Different Rank)...................:Auto
Twr2rd(Different Rank)...................:Auto
Trd2wr(Same/Diff Rank)..................:Auto
Dimm1 Clock Skew Control...............:Auto ps
Dimm2 Clock Skew Control...............:Auto ps
Motherboard Voltage Control
Voltage Type.………... Manual
CPU
CPU Vcore….……….........................: 1.38125V
CPU Termination…..... 1.200V*.......: 1.340V
CPU PLL…………………....1.500V*.......: 1.570V
CPU Referen.…………....0.755V*.......: .918V
MCH/ICH
MCH Core…………….....1.100V...........: 1.360V
MCH Reference….…….0.800V...........: .888V
MCH/DRAM Ref.…......0.900V...........: 1.050V
ICH I/O……………….....1.500V............: 1.570V
ICH Core…………...……1.100V............: 1.100V
DRAM
DRAM Voltage ……....1.800V............: 2.120V
DRAM Termination .…0.900V............: 1.050V
Channel A Reference 0.900V............: Auto
Channel B Reference 0.900V............: Auto
Advanced Settings
Limit CPUID Max. to 3.....................: [Disabled]
No-Execute Memory Protect............: [Enabled]
CPU Enhanced Halt (C1E)................: [Enabled]
C2/C2E State Support....................: [Disabled]
x C4/C4E State Support..................: [Disabled]
CPU Thermal Monitor 2(TM2) ...........: [Enabled]
CPU EIST Function.........................: [Enabled]
Virtualization Technology................: [Disabled]
Integrated Peripherals
Legacy USB Storage Detect ..............[Disabled]
Here's some useful info relating to reference volt settings
(edited from several PMs with Lsdme)
All reference voltages must be set with their respective "Controlling" Voltages at stock.
=============================================
CPU Termination (Vtt) Automatically changes the following if manually set >>>
CPU Reference Voltage (63% of Default Vtt/1.20) .76 ET
CPU Reference2 Voltage (67% of Default Vtt/1.20) .80 ET
MCH Reference Voltage (63% of Default Vtt/1.20) .76 ET
=============================================
DRAM Voltage Automatically changes the following if manually set >>>
MCH/DRAM Reference Voltage (50% of Default Dram Voltage)
DRAM Termination Voltage (50% of Default Dram Voltage)
Channel A Reference Voltage (50% of Default Dram Voltage)
Channel B Reference Voltage (50% of Default Dram Voltage)
==============================================
For example if you want to try 1.28 Vtt with .74 MCH Ref you must set Vtt to 1.20 first,
then go set MCH Ref to .74. Then go raise Vtt back to 1.28 and the MCH Ref will self adjust.
This is a table I created to bring some order to this madness:
Relationship of the Bios/ET6 values as a percentage of VTT (Cpu Termination) at 1.20 volts.
% of 1.20 values [before auto-adjustment]
55% = 0.660 || 60% = 0.720 || 65% = 0.780 || 70% = 0.840
56% = 0.672 || 61% = 0.732 || 66% = 0.792 || 71% = 0.852
57% = 0.684 || 62% = 0.744 || 67% = 0.804 || 72% = 0.864
58% = 0.696 || 63% = 0.756 || 68% = 0.816 || 73% = 0.876
59% = 0.708 || 64% = 0.768 || 69% = 0.828 || 74% = 0.888
I knew all of that ... its just that in my case, it doesn't matter if I individually set reference voltages to any value (trust me I've tried it many times just so I could bring CPU Term a little lower) and it still wont bring stability for lower CPU Term.
I do however manually set CPU Term to stock, CPU ref and MCH ref to stock (like you said) and then up CPU Term and both ref voltages would increase automatically with it at the % they need to be in relation to CPU Term.
I tried with lower CPU Term and 63% + for CPU Ref voltage up to 1v + in increments of one step and it didn't bring stability ...
As for onechop, its better if he leaves them linked @ 63% for starters and only after he gets a stable OC to try and lower CPU Term and fiddle with reference voltages to see if they do anything in his case.
Awesome OC BTW. Only 1.34V for 500Mhz is great and a PL of 9 is cool too... Won't even boot for me at that.. I need 1.48v
I guess I need that much more because I'm running 4 memory sticks and you ware most likely running 2.
Edited by Cryptedvick - 8/14/12 at 5:50pm
.
