Originally Posted by DiGiCiDAL
That just might be the nature of the chip... my 3570K is exactly the same thing... nice and smooth up to 4.6 - decent bump (1.37V) to hit 4.7 - well actually I can hit 4.7 @ 1.32V but it had errors about an hour into prime. To get to 4.8 is ridiculous... I need 1.44V to get there and 1.52V to get to 4.9 and even then it's not completely stable. Temps are higher with those increases, but still not so high that it's a problem with throttling... the chip is just voltage limited. Sounds like yours might be as well.
Although, also like me - you seem to have more than one chip running - so hopefully your other one is better (I know mine is).
I haven't tried to push it any higher yet (the delidded cpu), so I don't really know how far it will go. But as far as temperatures, at 1.380v vcore it's still only 74c with hyperthreading off so it's at least got a lot of headroom temperature wise. Not near as good as some I've seen, but not bad and a great improvement in temperatures compared to before.
The cpu in Merlin (not delidded) is OK, but not super. It likes a lot of volts as well. x45 clock is around mid 70's depending on Ambient while running 8K fft's w/AVX in Prime 95.
Probably when I get time I will move boards between the rigs so I don't have to pull the delidded cpu off and risk getting the metallic liquid TIM all over the place. Since the boards for all practical intents are identical UD5H's I won't be losing anything (but hours of time). It's a pita to pull the board out of the Switch, but still I'd rather go that route than swap cpu's.
I haven't decided how far I want to push the vcore on the delidded chip. I see people running crazy volts through them but I need for it to last me a while.
But all this demonstrates how Intel screwed us with that gap under the IHS and using paste TIM instead of solder or something with better heat conductivity. It's not that their TIM is bad, but TIM combined with the gap the adhesive creates keeps a lot of the heat from conducting out through the IHS.