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Segmenting the laptop lineup seems foolish to me - what will run on one portable won't run on another because its got a different architecture? Seems unlikely.I see it being more likely that they'd put an APU in the MBAs, and 13" MPB. they already suffer from low GPU power, due to there not being enough room for a real GPU.
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Try mine - core2 and GMA X3100. Bleh. at least I bumped it with 4GB ram and an SSD.
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Originally Posted by Blameless 
When Intel said that CISC vs. RISC didn't matter in 2000, they said so based on the fact that decode was only a tiny potion of die area. It's less now despite vastly increased complexity and performance. Yes, x86 has overhead that needs workarounds, but these workarounds are getting better and better, for less and less relative cost.
I recall AMD's claims regarding hammer and AMD64, and they were only true in the most niche of applications (the real world difference between many x86 and x86-64 programs that aren't memory limited is next to zero). I don't know weather this still has much bearing or not since K8 is quite old now, and all the overhead in question has evolved quite a bit.
Anyway, all this is academic. In the end, practical performance (and performance/watt, depending on use) is what matters. I'm not an engineer, I'm an end user. Show me a processor that can run the programs I use now (or roughly comparable equivalents), with a superior price/performance/power ratio (while reaching a necessary minimum performance, with a reasonable maximum budge) than something like Intel's Sandy or Ivy Bridge parts, and I will buy a system built around one today.
Notebooks are the primary systems for many, and are often called upon to do the same tasks as any other system.

When Intel said that CISC vs. RISC didn't matter in 2000, they said so based on the fact that decode was only a tiny potion of die area. It's less now despite vastly increased complexity and performance. Yes, x86 has overhead that needs workarounds, but these workarounds are getting better and better, for less and less relative cost.
I recall AMD's claims regarding hammer and AMD64, and they were only true in the most niche of applications (the real world difference between many x86 and x86-64 programs that aren't memory limited is next to zero). I don't know weather this still has much bearing or not since K8 is quite old now, and all the overhead in question has evolved quite a bit.
Anyway, all this is academic. In the end, practical performance (and performance/watt, depending on use) is what matters. I'm not an engineer, I'm an end user. Show me a processor that can run the programs I use now (or roughly comparable equivalents), with a superior price/performance/power ratio (while reaching a necessary minimum performance, with a reasonable maximum budge) than something like Intel's Sandy or Ivy Bridge parts, and I will buy a system built around one today.
Notebooks are the primary systems for many, and are often called upon to do the same tasks as any other system.
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Originally Posted by hajile 
Put simply, Intel said what unknowledgeable investors needed to hear. The truth is that the x86 ISA is still a huge burden especially in smaller chips. In addition, all the extra instructions have added even more to the x86 CISC decode burden. Read the article and you'll understand better. I'm happy to attempt to answer questions after that.
The performance difference when moving from 8 to 16 registers is huge. Two or three of the "general purpose" registers are already allocated for specific uses. This doesn't leave enough registers. Anyone who is familiar with assembly can testify to this fact.
The practical answer I'd that MIPS designs offer better gloating point performance. The future ProAPTIV architecture from MIPS offers the highest coremark per MHz of ANY design (an officially accepted score). In case you didn't know, Coremark is an industry accepted benchmark. It's only competitor is the ancient Dhrystone benchmark. At 2.5GHz, a ProAPTIV core should offer integer performance close to similarly clocked x86 competitors while still bring capable of offering decent float performance (while using half the die area as ARM A15).
Intel has good reason to be scared by ARM and MIPS as both are getting closer to the “fast enough” threshold and with MS supporting ARM (and Linux/Android supporting both), the threat is real even if it's not immediate.

Put simply, Intel said what unknowledgeable investors needed to hear. The truth is that the x86 ISA is still a huge burden especially in smaller chips. In addition, all the extra instructions have added even more to the x86 CISC decode burden. Read the article and you'll understand better. I'm happy to attempt to answer questions after that.
The performance difference when moving from 8 to 16 registers is huge. Two or three of the "general purpose" registers are already allocated for specific uses. This doesn't leave enough registers. Anyone who is familiar with assembly can testify to this fact.
The practical answer I'd that MIPS designs offer better gloating point performance. The future ProAPTIV architecture from MIPS offers the highest coremark per MHz of ANY design (an officially accepted score). In case you didn't know, Coremark is an industry accepted benchmark. It's only competitor is the ancient Dhrystone benchmark. At 2.5GHz, a ProAPTIV core should offer integer performance close to similarly clocked x86 competitors while still bring capable of offering decent float performance (while using half the die area as ARM A15).
Intel has good reason to be scared by ARM and MIPS as both are getting closer to the “fast enough” threshold and with MS supporting ARM (and Linux/Android supporting both), the threat is real even if it's not immediate.
On that note there are STILL operations that a 7410 G4 can do faster than a sandy chip per core (and people give the RAD750 a hard time). Take for example distriuted.net's rc5-72 - altivec/VMX IPC puts all others to shame. Makes me wonder where PPC could've gone if motorola had cared at all.
Edited by u3b3rg33k - 10/7/12 at 12:25pm











