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[Official] Delidded Club / Guide - Page 3112

post #31111 of 34163
Quote:
Originally Posted by Benjiw View Post

Yep, want proof? thumb.gif




Not at all necessary, but thanks.
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post #31112 of 34163
Quote:
Originally Posted by Arctucas View Post

Not at all necessary, but thanks.

I was just pimping out my system again because it was relevant but my gf's i5 will probably be delidded and the IHS glued back on.
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post #31113 of 34163
I might do bare die if and when I get another motherboard, but at this point, I am not feeling inclined to do the mod.
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post #31114 of 34163
Quote:
Originally Posted by Arctucas View Post

I might do bare die if and when I get another motherboard, but at this point, I am not feeling inclined to do the mod.

Hoping I can be the first to do it on a skylake chip using a shim or modding the base plate for the waterblock. Hoping to just shim it with 0.6mm of copper maybe less.
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post #31115 of 34163
Quote:
Originally Posted by bluej511 View Post

Or when people don't understand FACT its better to just stop talking.

You do understand that TIM/LM is actually a hindrance right? The thermal conductivity of TIM is anywhere between 5w/mK to 75w/mK. That sounds fantastic right? Wrong. The thermal conductivity of copper is 400w/mK. So in theory you don't want any TIM. You want the copper to sit flush against the DIE, with nothing in between, including air which has a thermal conductivity of .02w/mK.

Not hard to understand but i guess that eludes you. Finally post, hopefully it helps you understand why you want no gap anywhere in between thermal conductive materials.

Here's your problem....You're yet to figure out how there can be no gap between the IHS and die when there's sealant between the IHS and wafer. And your misunderstanding is providing comic relief for the savvy amongst us in this thread. Keep it up, I like a good laugh every now and then.
post #31116 of 34163
It just makes sense that there's a gap between IHS and die in the CPU's original state, and that's where the strangely high temperatures come from before delidding. In my mind, everything points to this.

First, just looking at a delidded CPU, it seems it's typical that people find a suspiciously thick amount of TIM stuck on the die (or IHS).

Next, it was shown in experiments that the original TIM that's used by Intel is actually a very good product. If that's the case, that you can get strongly improved temperatures by using (for example) NT-H1 after delidding points to there being a gap in the original state. The gap would explain why the temperatures are worse with Intel's TIM compared to NT-H1 etc.

Then, people often find suspiciously thick amount of silicone glue between IHS edges and PCB. This observation is a bit weak because a gap in that spot is normal as the IHS is supposed to be able to rest on top of the die's surface without touching the PCB, so a certain amount of gap between IHS and PCB that gets filled by glue has to always be there. It's still suspicious that this seems to be a bit thick often.
post #31117 of 34163
Quote:
Originally Posted by oparr View Post

[...]

I don't think I can find those experiments with Intel's TIM. I think it was somewhere here on this forum. The way I remember it, the person simply tried to put the IHS back on after cleaning off the glue, but not cleaning off the TIM.

You might be misunderstanding what people here think when they talk about a gap between die and IHS. It seems it's known that when you look at the parts when they are completely clean and without TIM and without glue, the gap you will see is between the IHS edges and the PCB while there's no gap at all between die and the middle of the IHS. At least this was the case a long time ago with 3570K and 3770K. There's was this post here four years ago which shows this in a neat .gif:

http://www.overclock.net/t/1313179/official-delidded-club-guide/1300#post_18419880



It makes it obvious how the parts are designed. In the design, it seems there's not supposed to be any gap between die and IHS. It's just that, this is not what happens in practice. After a CPU goes through manufacturing, it seems to usually end up with a gap there.

That's perhaps where the misunderstanding here happens? When people talk about there being a gap between die and IHS, they mean there's a gap in practice. They aren't talking about the theoretical design.
post #31118 of 34163
Quote:
Originally Posted by deepor View Post

I don't think I can find those experiments with Intel's TIM. I think it was somewhere here on this forum. The way I remember it, the person simply tried to put the IHS back on after cleaning off the glue, but not cleaning off the TIM.

You might be misunderstanding what people here think when they talk about a gap between die and IHS. It seems it's known that when you look at the parts when they are completely clean and without TIM and without glue, the gap you will see is between the IHS edges and the PCB while there's no gap at all between die and the middle of the IHS. At least this was the case a long time ago with 3570K and 3770K. There's was this post here four years ago which shows this in a neat .gif:

http://www.overclock.net/t/1313179/official-delidded-club-guide/1300#post_18419880



It makes it obvious how the parts are designed. In the design, it seems there's not supposed to be any gap between die and IHS. It's just that, this is not what happens in practice. After a CPU goes through manufacturing, it seems to usually end up with a gap there.

That's perhaps where the misunderstanding here happens? When people talk about there being a gap between die and IHS, they mean there's a gap in practice. They aren't talking about the theoretical design.

There are tools for measuring gaps, example;

https://en.wikipedia.org/wiki/Feeler_gauge

One can also use a piece of paper in this case. If the wafer is clean like this;

http://www.pbase.com/eldata/image/161511125/original

And the IHS is equally as clean where it counts most (no picture, use imagination), then it stands to reason that there can be no gap between IHS and die if when the IHS is placed over the die, there is a gap all around between IHS and wafer. The IHS cannot levitate, it has to be resting on the die. The base of the IHS has to be sanded down in the unlikely event that there is no gap between IHS and wafer.

This is what one should ascertain before applying the new TIM and sealant. Pressure has to be applied while the sealant is curing so that the sealant thickness between IHS and wafer, where it counts most, is no greater than the original gap. Excess sealant will be forced out of the gap on both sides, while in its liquid state, long before the sealant starts to cure.

Now off to watch something on Netflix.
post #31119 of 34163
Well... that's simply not what happens in practice in Intel's factories. There seems to be a gap there after manufacturing. I don't know what they are doing. Perhaps they don't use enough pressure when installing the IHS onto the CPU? Or perhaps they use enough pressure but the plunger that installs the IHS plunges down hard for just a split second, and then it pulls away immediately afterwards and there's no time for the excess TIM and glue to get pushed out of the way?
post #31120 of 34163
Quote:
Originally Posted by deepor View Post

Well... that's simply not what happens in practice in Intel's factories. There seems to be a gap there after manufacturing. I don't know what they are doing. Perhaps they don't use enough pressure when installing the IHS onto the CPU? Or perhaps they use enough pressure but the plunger that installs the IHS plunges down hard for just a split second, and then it pulls away immediately afterwards and there's no time for the excess TIM and glue to get pushed out of the way?

Dunno, there is obviously an issue because once we remove the sealant the issue is gone so.
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