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[TigerDirectTV] AMD FX CPU Talk with Brent - Page 7

post #61 of 119
Quote:
Originally Posted by Demonkev666 View Post

you are some what some where wrong in this comment.
Let me guide you to a better answer
I've been playing with an FX since I bought one.
The 18% is TLB's in FX are up the front end when a single thread is used it also gets to use both form each core of these for the single thread.
pile driver cores have added TLB's givin the 15%-17 increase in single thread
Why would the translation lookaside buffer fix the issue?
Quote:
Secondly the chip is more of a hybrid design it will split the front end from a 4 down to a 2 way decoder for each core in the module.
how ever this usually happens when the the registry files inside the chip have to completely write different programs to work on.
you'll see a 33% loss in single thread. when running dual threads that are not similar data in a module.
If I run cinebench 11.5r normally I get about 0.76 for single thread but when I run IntelBurnTest on the other core with cinebench 11.5r single module I get 0.58 in the single thread test. the MP ratio is at 8.0+ then not 6.4 or 6.6.
the FlexFPU is dual threaded the single scheduler is the the main problem of the slow down. too much waiting for data.
I agree that steamroller should be a nice jump.
The IPC claim the first is Clock vs clock 7%
The later is TDP vs TDP clock improvements

I got my 18% number from here: http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/9
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post #62 of 119
Quote:
Originally Posted by Homeles View Post

Why would the translation lookaside buffer fix the issue?
I got my 18% number from here: http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/9

I believe it has to do with cache misses going into the TLB's Then to Ram and since phenom II has 72 entries vs 32 entries for FX there was a large a gap.
pile driver cores now have 64 entries instead.

the only thing that gets me in anatechs article there is he says SMT adds to IPC ? :-/
Quote:
Almost 1.4 instructions per clock cycle are retired and if you add SMT (Simultaneous Multi Threading), another 0.4 IPC flows through a single core
    
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post #63 of 119
Why wouldn't it?
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post #64 of 119
Quote:
Originally Posted by Homeles View Post

Why wouldn't it?

it's two threads ? not one.
    
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post #65 of 119
Still one core.
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post #66 of 119
Quote:
Originally Posted by Homeles View Post

Still one core.

your point ? FX is one instruction cache to two threads too. Instructions Pre clock < IPC
    
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post #67 of 119
I... I don't even know what to say to that.
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post #68 of 119
Quote:
Originally Posted by Demonkev666 View Post

Instructions Pre clock > IPC

Fixed.

You have no idea how much IPC my PC has, it puts all super computers put together to shame. Then I turn it on...
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post #69 of 119
Quote:
Originally Posted by Liranan View Post

You have no idea how much IPC my PC has, it puts all super computers put together to shame. Then I turn it on...
3 macro-instructions and less. Also, it doesn't put any supercomputers to shame unless we are talking about 1970s to 2000s computers.
Edited by Seronx - 10/7/12 at 11:40pm
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post #70 of 119
Quote:
Originally Posted by Seronx View Post

3 macro-instructions and less. Also, it doesn't put any supercomputers to shame unless we are talking about 1970s to 2000s computers.

We definitely need sarcasm tags...
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