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[Phoronix] AMD Drops Steamroller "bdver3" Compiler Support

post #1 of 34
Thread Starter 
Here, something to counter the source-less OBR claim of a delay in Steamroller-architecture based APU or CPU. This happened just 6 days ago.

Readers might be confused by the use of the word "drop" in the article title - this refers to the addition of, and not the removal of support.

SOURCE LINK
Quote:
As first spotted via my Anzwix system, Ganesh Gopalasubramanian of AMD published the first patch work concerning "bdver3" enablement to gcc-patches on Thursday morning. "The attached patch (Patch.txt) enables the next version of AMD's bulldozer core. A new file (bdver3.md) is also attached which describes the pipelines."

As with previous generations, this compiler tuning/optimization support for next year's AMD hardware is being called "bdver3" in a similar naming convention to the original Bulldozer CPUs ("bdver1") and the new Piledriver / Bulldozer 2 support ("bdver3"). The bdver3 GCC patch in its early form copies most of the tuning work from bdver2 but the pipelines have already been modelled after the new Steamroller core.

The bdver2 support within this leading open-source code compiler super-set the following instruction set extensions: BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, and ABM. The current bdver3 family support is also setting these same instruction set extensions without anything new for the moment, aside from the pipeline remodelling.

Edited by xd_1771 - 10/17/12 at 5:17pm
post #2 of 34
Nice to hear new of progress.
post #3 of 34
Good to hear! thumb.gif
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post #4 of 34
Quote:
Fetching is done every two cycles rather than every cycle and two decode units are available. The decode units therefore decode four instructions in two cycles.

Interesting.

Looks like no AVX2 support, at least so far. I don't think Steamroller will be getting it — AMD just hasn't specifically stated it yet.
Edited by Homeles - 10/17/12 at 5:31pm
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post #5 of 34
Basicly interlacing but for decoding .grin
post #6 of 34
Whatever this is, it looks good!
post #7 of 34
finally they are doing something right: compiler support for the instructions set on their new CPUs...
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post #8 of 34
Fun fact — GCC first implemented support for Bulldozer (bdver1) on March 25, 2011 with version 4.6.0. Bulldozer launched 7 months later. So a September 20, 2012 update for bdver3 means an April release, right? thumb.gif

Just kidding. But it does suggest that AMD is not falling behind.
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post #9 of 34
I'm curious if PCSX2 devs will see anything nice to take advantage of from these new instruction sets, since AVX is only useful in software mode and not hardware mode. Definitely interested me, that's for sure.
    
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post #10 of 34
In Layman's terms please? rolleyes.gif
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