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[PCM] Intel Shipping First Xeon Phi Coprocessors - Page 5

post #41 of 67
Quote:
Originally Posted by DuckieHo View Post

Yes, it supports x86 but not all the additional instruction sets.
Read: http://www.brightsideofnews.com/news/2012/7/13/xeon-phi-lacks-binary-compatibility2c-breaks-amd64-conventions.aspx

I find this amusing.
   
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post #42 of 67
Quote:
Originally Posted by Homeles View Post

Ha! Speak of the devil — I just asked where Intel's MIC was earlier today.
That memory bus is wide. Hello there, 512 bit bus. Running at 1375MHz too. Not bad at all for Intel's first foray into the market.
That die is a monster. Gotta be around 600mm², and on 22nm too. Wish I could look at the cores more closely — even the high rez photos are blurry.
It's also very different from the Aubrey Isle die, which is (apparently?) Knight's Corner's predecessor.
intel_aubrey_isle_coprocessor.jpg

Considering the GK110, which delivers even more flops, runs on a 384bit bus. I'm not sure why Intel will choose to implement a 512bit bus, as this surely takes a lot of die space to implement, which can't be good for yields and cost.
 
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post #43 of 67
Quite an impressive double precision performance, considering its said to be x86 compatible.
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post #44 of 67
This is very interesting but it depends on what can be done with it. If it can't match the flop output of a Tesla or AMD's offerings then they still are no use, despite being x86, and paper means nothing.
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post #45 of 67
Quote:
Originally Posted by zooterboy View Post

Yes, this is what TDP is. Well, more accurately, it's the maximum wattage the cooling solution is designed to dissipate, at full load.
Edit: Sorry, meant to say maximum wattage it will consume/need to be dissipated.
Maybe you should read what I posted because what you just said is exactly my point.
Not quite.

TDP is short thermal design power. It is not the maximum cooling required for a chip rather it is the maximum cooling required for a chip in "real world use". Each company has a different way of defining "real world use".



For example, the Nvidia GTX480 has a TDP of 250w. However, the card could draw over 300w running certain stress tests.



Quote:
Originally Posted by pisstaker View Post

Considering the GK110, which delivers even more flops, runs on a 384bit bus. I'm not sure why Intel will choose to implement a 512bit bus, as this surely takes a lot of die space to implement, which can't be good for yields and cost.
It depends on the architecture of the chip as well. You can't just look at memory bus and FLOPs alone.
Quote:
Originally Posted by Liranan View Post

This is very interesting but it depends on what can be done with it. If it can't match the flop output of a Tesla or AMD's offerings then they still are no use, despite being x86, and paper means nothing.
Actually, x86 compatibility is actually a big thing. HPC code is already usually hand optimized. It's easier to migrate and re-optimizing existing HPC software on the same ISA since there is familiarity and fewer differences. Moving to Tesla or FireStream requires vastly more work.
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post #46 of 67
Quote:
Originally Posted by DuckieHo View Post

It depends on the architecture of the chip as well. You can't just look at memory bus and FLOPs alone.
Actually, x86 compatibility is actually a big thing. HPC code is already usually hand optimized. It's easier to migrate and re-optimizing existing HPC software on the same ISA since there is familiarity and fewer differences. Moving to Tesla or FireStream requires vastly more work.

What I meant was that they can state all they want on paper but it depends on the performance whether it's a decent product or not. AMD's chips are more powerful on paper but in certain tasks nVidia's easily outdo them. I don't know whether this is driver support, optimisation or the architecture simply being more powerful. I suppose it's a combination of all three.

Regardless, this is really interesting. I would like to know which team developed it and where it's being made.

Something else I just thought of is which parts of the x86 they didn't include in this thing and whether it would have been any mode powerful if it ran OpenCL, if such a comparison can be made at all.
Edited by Liranan - 11/13/12 at 3:25pm
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post #47 of 67
But can it run Metro 2033Crysis?
Quote:
Intel said that the "more than 50" OEM partners in the HPC and supercomputer segments currently building Xeon Phi systems include Acer, Appro, Asus, Bull, Colfax, Cray, Dell, Eurotech, Fujitsu, Hitachi, Hewlett-Packard, IBM, Inspur, NEC, Quanta, Supermicro, and Tyan.

Nvidia just pulled its CUDA cores closer to it's body. This being x86-compatible can't be good for Nvidia's proprietary tools.
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post #48 of 67
Quote:
Originally Posted by Liranan View Post

What I meant was that they can state all they want on paper but it depends on the performance whether it's a decent product or not. AMD's chips are more powerful on paper but in certain tasks nVidia's easily outdo them. I don't know whether this is driver support, optimisation or the architecture simply being more powerful. I suppose it's a combination of all three.
Regardless, this is really interesting. I would like to know which team developed it and where it's being made.
Something else I just thought of is which parts of the x86 they didn't include in this thing and whether it would have been any mode powerful if it ran OpenCL, if such a comparison can be made at all.

However, the most important aspect of HPC performance is the software, not just the hardware. It does not matter if you have a 10x faster hardware if developers have not had the experience to optimize their code on it. With HPC, the software has to be customized to the hardware to extract performance.... this is hard. So providing existing x86 developers with a similar environment and allowing them to use the same tools is a hugely important.


Read this for a brief overview on the importance of code optimization in HPC: http://www.tomshardware.com/reviews/xeon-phi-larrabee-stampede-hpc,3342-5.html


OpenCL is a framework.... language/API and is support by Intel while x86 is a instruction set. The advantage of the Phi is that developers do not have to learn OpenCL, they can continue what they are basically doing today with existing code and tools. It also allows developers to program to-the-metal more easily since they are not relying on APIs as much.
Edited by DuckieHo - 11/14/12 at 7:23am
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post #49 of 67
Can anyone tell me what they can be used for ?
post #50 of 67
Quote:
Originally Posted by JustTellMe View Post

Can anyone tell me what they can be used for ?


Stuff like that
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