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[PCM] Intel Shipping First Xeon Phi Coprocessors - Page 7

post #61 of 67
Quote:
Originally Posted by DuckieHo View Post

To be more explicit, I don't see consumers needing dedicated co-processors running a seperate OS within their host systems.
Consumers are already using manycore co-processors (GPUs) with a very well established eco-system supporting a wide range of tasks.
I can agree with that.

Supposedly Larrabee-based graphics/co-processors (the line is rather blurry) will be making it into Skylake. I'd imagine that consumers would take be able to take advantage of the hardware acceleration, while developers would be able to take advantage of the x86 instruction set. MIC will be similar in these sense that it is geared for tackling high-bandwidth workloads, but less versatile/more specialized.
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post #62 of 67
Are intels cores OoO capabile? Do they have floating point units? In short, are they CPU processors or general purpose ones?
post #63 of 67
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Originally Posted by zooterboy View Post

Yeah, actually I do understand them.
Why don't you enlighten us all as to how TDP wouldn't be an accurate estimation of power consumption?
So, my 65 watt SB system pulls about 50 watts from the wall, and my 130 W 920 system pulls well over 200. If you'll notice, nearly every Ivy bridge CPU has a TDP of 55 or 77 watts. This means they either pull 55 or 77 watts. Nothing more, nothing less. Oh wait, that's stupid.

For someone who understands TDP, you should come understand my Kill-a-Watt meter...
post #64 of 67
Quote:
Originally Posted by mothergoose729 View Post

Are intels cores OoO capabile? Do they have floating point units? In short, are they CPU processors or general purpose ones?

Phi's cores are not OoOE capable... and they don't need to be. OoOE increases thread performance at the cost of higher power consumption. Since this is a manycore processor, the power budget is better off spent on adding more cores rather than adding higher performing cores.


THG has a good write up here: http://www.tomshardware.com/reviews/xeon-phi-larrabee-stampede-hpc,3342.html
•An in-order, dual-issue x86 design with 64-bit support
•Four threads per core, and up to 61 cores per coprocessor
•512-bit SIMD for wider vectors
•512 KB of L2 cache per core (up to 30.5 MB per Xeon Phi)
•22 nm tri-gate transistors
•Red Hat Enterprise Linux 6.x or SuSE Linux 12+ support
•6 or 8 GB of GDDR5 per card

The Vector Processing Unit (VPU) is the main workhorse. The x87 is the FPU for the x87 FP instructions (but I'm not sure the difference between "x87" and "x87 RF".)
Intel's docs: http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-codename-knights-corner
"Vector Processing Unit

An important component of the Intel Xeon Phi coprocessor’s core is its vector processing unit (VPU), shown in Figure 5. The VPU features a novel 512-bit SIMD instruction set, officially known as Intel® Initial Many Core Instructions (Intel® IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers."


Edited by DuckieHo - 11/14/12 at 9:25am
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post #65 of 67
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Quote:
Originally Posted by DuckieHo View Post

Correct, Intel's Larrabee project to make a GPU/GPGPU based on x86 cores failed after 5-6 years. They then decided to use the technology instead solely for the GPGPU part and rebrand the thing a Many Integrated Core (MIC).

1st gen Larrabee was going to be a discrete consumer gpu, it was cancelled. 2nd gen Larrabee was going to be used in a co-processor(Knights Ferry), but according to semi-accurate it wouldn't have been software compatible with 3rd gen and later Larrabee, it too was cancelled. Which brings us to Knights Corner/Xeon Phi, 3rd generation Larrabee.

Unlike 1st gen Larrabee, Knights Ferry/Knights Corner have no graphics hardware so can't drive a monitor. However, it appears Intel still plans to integrate larrabee cores into their CPUs(If Intel had kept their original roadmap it would have happened with Sandy Bridge). I imagine they would replace the Execution Units in current Intel HD graphics. So we may still see it powering graphics, just not as a discrete card.
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post #66 of 67
Excellent information Duckie, thank you very much.

So, this is Intel's idea of HSA? Very interesting and clever!
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post #67 of 67
Quote:
Originally Posted by DuckieHo View Post


•Four threads per core, and up to 61 cores per coprocessor

Holy Crap... 4 threads per core? I Thought I´ve never see this day on a x86 CPU(SPARC T3 processors can do 8 per core).....

have you guys heard about ScaleMP? they have a Software SMP hypervisor that will allow a dual socket Xeon system with Phi co processors to appear like a Huge SMP to the Linux system, like a Huge Single Image System with a total of 66 Cores and 136 Gb of RAM... http://goparallel.sourceforge.net/virtualized-symmetric-multiprocessing-eases-mic-transition/

and yes it will Run Crysis(wont mean much as Crysis sucks at multithreading), CineBench and the system can use all of its memory and cores at the same time,
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