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[Xbitlabs]Intel’s Haswell to Feature Secrete Weapon: Integrated Voltage Regulator. - Page 8

post #71 of 163
Quote:
Originally Posted by Skylit View Post

I don't care about overclocking. I just want a fast, low power consumption processor that can run games at my desired framerate.

I hate this kind of attitude...

Just because you don't care about it doesn't mean others won't.
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post #72 of 163
Quote:
Originally Posted by Artikbot View Post

Quote:
Originally Posted by 47 Knucklehead View Post

I guess I'm the only one who, as an overclocker, is slightly concerned that this will actually be a negative thing ...

It will. Say goodbye to your overclocks.

First they locked down bclk. Then multiplier. And next comes the power delivery.


I see where is this all leading to.



So much misconception in this thread... LOL!

Again... - VRM IS NOT IN CPU.... VRM CONTROL IS.

You cannot fit power phases into CPU... ROFL!

You can fit IC control functions into CPU though.

This has no bearing on CPU temp at all.

Haswell can OC just fine.
post #73 of 163
Took some quotes from the Anandtech analysis:

"The decode stages are very power hungry so being able to skip them is a boon to power efficiency."

Less heat produced?

"The other major addition to the execution engine is support for Intel's AVX2 instructions, including FMA (Fused Multiply-Add). Ports 0 & 1 now include newly designed 256-bit FMA units. As each FMA operation is effectively two floating point operations, these two units double the peak floating point throughput of Haswell compared to Sandy/Ivy Bridge"

2x FPU throughput =D

"The three clock domains in Haswell are roughly the same as what they were in Nehalem, they just all happen to be on the same die. The CPU cores all run at the same frequency, the on-die GPU runs at a separate frequency and now the L3 + ring bus are in their own independent frequency domain.

Now that CPU requests to L3 cache have to cross a frequency boundary there will be a latency impact to L3 cache accesses. Sandy Bridge had an amazingly fast L3 cache, Haswell's L3 accesses will be slower.

The benefit is obviously power. If the GPU needs to fire up the ring bus to give/get data, it no longer has to drive up the CPU core frequency as well. Furthermore, Haswell's power control unit can dynamically allocate budget between all areas of the chip when power limited.

Although L3 latency is up in Haswell, there's more access bandwidth offered to each slice of the L3 cache. There are now dedicated pipes for data and non-data accesses to the last level cache.

Haswell's memory controller is also improved, with better write throughput to DRAM. Intel has been quietly telling the memory makers to push for even higher DDR3 frequencies in anticipation of Haswell. "

Core clock and L3 clock are separate now, meaning that if the lowest common denominator on an individual sample is the L3 cache, it won't bottleneck the max core overclock. I'm assuming.

I'm pretty stoked by all this!
Edited by Scorpion667 - 12/28/12 at 12:04pm
    
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post #74 of 163
Quote:
Originally Posted by Scorpion667 View Post

I didn't say it ran at higher voltage I said it ran hot at higher voltages. I.E put a 2500k and a 3570k at 1.35v and you can guess which will run hotter.
I do see your point though.
My apologies, I read it wrong, and yes a 2500k @1.35 volts will run cooler than ivybridge@1.35 volts(unless you're delidded) but the volts to reach the same overclock are generally quite a bit lower on ivybridge
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post #75 of 163
Quote:
Originally Posted by DuckieHo View Post

To be clear, Intel didn't "lock down" bclk.... they just linked more components to it to reduce cost and complexity.

But they took us the power of setting it manually to adjust processor/memory/system link speed. And that, sucks.

AMD FM1/FM2 platforms at least let you rise it a bit... Even if it's a 12-15% in most cases. But it's something.
   
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post #76 of 163
Quote:
Originally Posted by Artikbot View Post

But they took us the power of setting it manually to adjust processor/memory/system link speed. And that, sucks.
AMD FM1/FM2 platforms at least let you rise it a bit... Even if it's a 12-15% in most cases. But it's something.

FM1 and FM2 can crank the baseclock when the HD's are in IDE mode.
(My) Llano machine would max out the internal pll clock at 137bclk. Trinity machine gives me 96-106 to play with for fine tuning. (AHCI limited, not mobo/a10)

Anyone catch the "secrete" spelling error? lol

I think scorpion667 has the right idea with post 73. Good chance by unlocking lv3 theres extra power savings, better overclocking, along with the vrm controller on die should make this a great lappy chip. I see idle/gpu power consumption dropping because of this. Crank up the lv3 frequencies on the desktop and sacrifice the power savings for better performance.
Also, when was intel pushing the limits of mem frequencies? I thought it was really only noticeable on amd FM platforms/mildly effective on FX series due to the lower throughput of AMD's mem controller vs intel's? I can't wait for ddr4 to fix the throughput issue for the apu's.
post #77 of 163
Quote:
Originally Posted by Yeroon View Post

Anyone catch the "secrete" spelling error? lol .
I did; I thought that secreting weapons sounded dangerous.
post #78 of 163
Quote:
Originally Posted by Scorpion667 View Post

Core clock and L3 clock are separate now, meaning that if the lowest common denominator on an individual sample is the L3 cache, it won't bottleneck the max core overclock. I'm assuming.
I'm pretty stoked by all this!
The µArch dude that did the AMA said Anand got the reasoning behind the L3 wrong, but wouldn't elaborate much because of confidentiality. My guess is that each core gets it's own vcore and clock domain, and can step up or down independently of the other cores according to load and budgeted TDP. Would mean at least 6 clock domains instead of the 3 Anandtech suggested.

http://www.reddit.com/r/IAmA/comments/15iaet/iama_cpu_architect_and_designer_at_intel_ama/c7mqnzq
Edited by TranquilTempest - 12/28/12 at 1:24pm
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post #79 of 163
Quote:
Originally Posted by TranquilTempest View Post

The µArch dude that did the AMA said Anand got the reasoning behind the L3 wrong, but wouldn't elaborate much because of confidentiality. My guess is that each core gets it's own vcore and clock domain, and can step up or down independently of the other cores according to load and budgeted TDP. Would mean at least 6 clock domains instead of the 3 Anandtech suggested.
http://www.reddit.com/r/IAmA/comments/15iaet/iama_cpu_architect_and_designer_at_intel_ama/c7mqnzq

To have independent core clocking...... I believe that would require OS support to be used effectively.
Once again...
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Once again...
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post #80 of 163
No matter what the specs say we will either have low overclocks either blowing up CPU-s.
Those circuits that will "control" the VRM-s will have feed-backs in relation to the state of the CPU itself and most probable less headroom will be available than with the actual chips .
They did this for "granularity" ,they say nowhere that the overclocking will be better.
Sorry ,but this CPU-s will be expensive and bad overclockers
The generation that comes after this one will add the lack of sockets.
Intel is in the process of nailing it for market control and profits .
   
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