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post #221 of 595
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Originally Posted by KyadCK View Post

Quote:
Originally Posted by dlee7283 View Post

Quote:
Originally Posted by KyadCK View Post

Quick question for you here.

990FX allows for 32GB of addressable ram. It gives out 40ish PCI-e lanes, and comes with 6 SATA3 ports stock. It can do full x8/x8/x8/x8.

Piledriver fixed a large number of multi-GPU issues, which means it was the CPU, not the chipset.

So knowing this, what exactly is bad about the chipset? I hear all these complaints about it, but they all boil down to "it;'s bad for multi-gpu", which is bull since if it was the chipset, PD couldn't have done any better then BD, but it did. (and yes, the 8150 and 8350 both have a 2.6Ghz HyperTransport)

I think the problem is HyperTranport itself, AMD started using it in K8 and it was shown to be much better than their I/O for Socket A. It was really good for the time, especially in early PCIe days. I think AMD needs to abandon it like Intel did and start using something similar to DMI. Their processors can't get the memory bandwidth needed to coexist properly and I feel HT is a culprit in some of it. The switch from FSB to a different link from intel is what really put them over the top. If AMD used a better optimized I/O link I am sure Piledriver would handle Multi-GPU setups neck and neck with Intel.

Some AMD engineer back in 2003 probably saw the eventual limitations of HT but everyone saw it as a good 10 years down the line until they needed something else. Fast forward to 2013 and you have that problem since AMD kept it to maintain better compatibility across the board and they didn't address it in 15h and now its biting them in the high end market badly. 12h and 14h are still more than fine with HT but with 15h is not.

OK, well, you seem to be under the misconception that Memory IO is handled by the Physical Northbridge through HyperTransport.

Not only does AMD have the memory controller on the chip itself, they did it first and Intel followed their lead.

This is how AMD's IO is structured:


HyperTransport is a big gate to everything that's on the motherboard that isn't RAM. Basicly, The Northbridge as you know it is a massive Switch to handle bandwidth between HyperTransport and PCI-e devices. The Soughtbridge is also connected to the Northbridge via PCI-e, which is why tinkering with PCI-e speeds can cause harddrive problems.

AMD's IO makes a lot more sense if you understand networking. Believe me. That doesn't mean It couldn't be made better by moving everything to the die (shorter distances are almost always better), it just means it's much easier to go "ooooh, now I know why they did it that way".

Why would you say that he has that misconception ? I didn't understand that, I think he has the right idea. The problem is that AMD's platforms have the PCIe controller on the Northbridge, which is not only outside the CPU, it is linked to it by an outdated link called HyperTransport.
 
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post #222 of 595
Quote:
Originally Posted by dlee7283 View Post

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Originally Posted by KyadCK View Post

OK, well, you seem to be under the misconception that Memory IO is handled by the Physical Northbridge through HyperTransport.

Not only does AMD have the memory controller on the chip itself, they did it first and Intel followed their lead.

This is how AMD's IO is structured:

basically Hypertransport needs a protocol for improved scalability according to this. Could be be in direct connection to the multi card gpu bottleneck problem with AMD so maybe its more of the need for a better protocol in handling the PCIe lanes even though in theory they aren't fully saturated in some cases.

http://www.hypertransport.org/docs/uploads/Extending_HT_Protocol_for_Improved_Scalability_Slides.pdf

Everything needs improved scalability. tongue.gif

Anyway, you realize Intel has to do this same sort of thing and can only cut out one step in the process, right? They just moved this onto the die instead of leaving it on the motherboard. Regardless, Intel can't hotwire PCI-e devices straight to the CPU, it doesn't work that way. They all go to an internal switch. Now, their switch is better then AMD's, obviously, but it's the same idea.

And not to step on intel people's toes, but all that USB3.0 support, PCI-e 3.0 support, etc? That's just them adding a Intel USB3.0 controller on the die and bolting it to their version of AMD's northbridge. No special work goes into adding compatibility. Even at the motherboard layer, computers are legos. Putting an Intel USB3.0 chip on an AMD motherboard and giving it a PCI-e x1 to the northbridge will get the same results.

Anyway, what we're discussing at this point is no longer a Chipset problem. This is protocol and "why don't they move it to the CPU already" problem. The "chipset" is just a big switch now anyway. Speaking of, didn't FM2 move it to the CPU? Someone needs to test 7970 xfire on Trinity vs Sandy (x8/x8 PCI-e 2.0 for both) and see what's up.
Quote:
Originally Posted by tpi2007 View Post

Why would you say that he has that misconception ? I didn't understand that, I think he has the right idea. The problem is that AMD's platforms have the PCIe controller on the Northbridge, which is not only outside the CPU, it is linked to it by an outdated link called HyperTransport.

I misunderstood DMI to mean Direct Memory Interface instead of Direct Media Interface, which in retrospect makes a lot more sense. Stupid acronyms.
Edited by KyadCK - 1/25/13 at 3:13am
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post #223 of 595
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I misunderstood DMI to mean Direct Memory Interface instead of Direct Media Interface, which in retrospect makes a lot more sense. Stupid acronyms.

Oh yes, that is confusing, I fully agree, I had a hard time memorizing that we now had another DMI with a different meaning, Intel surely could have come up with a more diferentiating name. thumb.gif
 
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post #224 of 595
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Originally Posted by tpi2007 View Post

Why would you say that he has that misconception ? I didn't understand that, I think he has the right idea. The problem is that AMD's platforms have the PCIe controller on the Northbridge, which is not only outside the CPU, it is linked to it by an outdated link called HyperTransport.

Thank you for seeing where I am coming from even though I appreciate all input as we all just want to learn more

basically this is the issue with Hypertranport

According to the data sheet the scalability is limited to 32 nodes with HT

this seems to have been addressed in in Intel's QPI sheet which says instead of using slower higher latency DRAM to address these functions(which Hypertranport uses), low latency cache is used instead, which might explain why Intel now has a large Level 3 cache when they never used it in the past.

Intel must be using its smaller level 2 to address direct memory communication with the CPU while the L3 is doing other I/O functions, since I/O functions need more than say 256kb which is fine on a properly optimized processor to handle that direct communication with the memory but not the rest of the system.

So it looks like AMD has all this level 3 cache that basically goes to waste as HT is using system memory to handle these functions, and which might also explain why the Athlon II X4 which has no level 3 isnt much slower than a Phenom II.

So if AMD had its own version of QPI it could use it's L3 to actually improve performance and scalability since its lower latency(even though higher than Level 1 or 2 is still much faster than using system memory to handle this.
Edited by dlee7283 - 1/25/13 at 3:22am
    
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post #225 of 595
I'm sure AMD are working on an upgrade to HyperTransport.
I'd love to see the CPU market trade blows like in the GPU market. AMD need more money.
Edited by xeekei - 1/25/13 at 3:36am
post #226 of 595
Quote:
Originally Posted by dlee7283 View Post

Quote:
Originally Posted by tpi2007 View Post

Why would you say that he has that misconception ? I didn't understand that, I think he has the right idea. The problem is that AMD's platforms have the PCIe controller on the Northbridge, which is not only outside the CPU, it is linked to it by an outdated link called HyperTransport.

Thank you for seeing where I am coming from even though I appreciate all input as we all just want to learn more

basically this is the issue with Hypertranport

According to the data sheet the scalability is limited to 32 nodes with HT

this seems to have been addressed in in Intel's QPI sheet which says instead of using slower higher latency DRAM to address these functions(which Hypertranport uses), low latency cache is used instead, which might explain why Intel now has a large Level 3 cache when they never used it in the past.

Intel must be using its smaller level 2 to address direct memory communication with the CPU while the L3 is doing other I/O functions, since I/O functions need more than say 256kb which is fine on a properly optimized processor to handle that direct communication with the memory but not the rest of the system.

So it looks like AMD has all this level 3 cache that basically goes to waste as HT is using system memory to handle these functions, and which might also explain why the Athlon II X4 which has no level 3 isnt much slower than a Phenom II.

So if AMD had its own version of QPI it could use it's L3 to actually improve performance and scalability since its lower latency(even though higher than Level 1 or 2 is still much faster than using system memory to handle this.

To give you an idea the latency's you're looking at:


Anyway, the only things listed different from AMD's methods here are:

Use Cache over RAM
Move it to on the Die
Faster protocol

All of which is basically "lower the latency". Still no chipset issue besides the fact the chipset is on the motherboard. Really, when discussing this, maybe it's time to be looking at Trinity instead of Piledriver. The chip was moved onto the die (that's one step forward), but both sockets are to stay around for a while. (at least one more year on AM3+, 2 more I think for FM2)

Also, none of this explains PD's magical ability to handle multi-GPU better the BD. Hypertransport didn't change, and that's what you're saying is the problem here. So what else got tweaked and what step are we missing that changed.
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post #227 of 595
Quote:
Originally Posted by KyadCK View Post

Everything needs improved scalability. tongue.gif

Anyway, what we're discussing at this point is no longer a Chipset problem. This is protocol and "why don't they move it to the CPU already" problem. The "chipset" is just a big switch now anyway. Speaking of, didn't FM2 move it to the CPU? Someone needs to test 7970 xfire on Trinity vs Sandy (x8/x8 PCI-e 2.0 for both) and see what's up.
I misunderstood DMI to mean Direct Memory Interface instead of Direct Media Interface, which in retrospect makes a lot more sense. Stupid acronyms.

Virgo is using an AMD inhouse PCIe link instead of a hypertransport so the cpu is able to access the gpu directly and more effeciently, but there is no level 3 on Trinity so it must still be using higher latency system memory to handle certain protocols instead of the level 3 cache which intel shows is needed for scalability. So AMD has the CPU staring right at the GPU but that wasn't even the real problem.

AMD addressed every issue but the one that would have been the simpliest, use Level 3 for I/O. And why use outdated HT on your high end flagships but on your mid you use something that in theory is better?
    
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post #228 of 595
Quote:
Originally Posted by KyadCK View Post

To give you an idea the latency's you're looking at:


Also, none of this explains PD's magical ability to handle multi-GPU better the BD. Hypertransport didn't change, and that's what you're saying is the problem here. So what else got tweaked and what step are we missing that changed.

Its IOMMU,probably a better implementation than Bulldozer.
Quote:
The HyperTransport™ specification requires devices (especially tunnels and bridges) to interoperate with
other devices in ways that ensure correctness and maintain performance. Among other requirements,
HyperTransport™ devices must make certain transaction ordering guarantees and must ensure they operate
without deadlocks.
A key requirement in the HyperTransport™ specification is that posted requests must be able to pass nonposted requests. The introduction of the IOMMU, however, means that posted requests (e.g. writes to memory)
may spawn non-posted requests (I/O page table walks) that must complete before the posted request can be
allowed to progress further.
To avoid deadlocks, the IOMMU requires a dedicated virtual channel for its I/O page table walk requests. This
ensures that, the IOMMU’s page table walks on behalf of posted requests can complete, regardless of the
completion status of other non-posted traffic in the fabric. The IOMMU also requires that the host bridge
process its requests without spawning any requests to other devices. In other words, the IOMMU’s table
structures must be located solely in system memory.

The IOMMU can share its virtual channel with other traffic as long the other traffic is also guaranteed to make
forward progress. In practice, this means that any other devices sharing the IOMMU’s page walk channel must
also restrict their non-posted traffic solely to accessing system memory.

To allow the IOMMU to support different AMD processors with different isochronous capabilities the
IOMMU control registers contain bits that control the state of the PassPW bits, the coherent bit and the
isochronous bit in the HyperTransport™ link read request issued by the IOMMU.

Edited by dlee7283 - 1/25/13 at 4:10am
    
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post #229 of 595
New Review by Logan

FX 8350 OC vs I5 3570K OC Using GTX 670

http://www.youtube.com/watch?v=4et7kDGSRfc&feature=player_embedded
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post #230 of 595
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I think the problem with Piledriver is that it gives performance enthusiasts were already use to in 2009. Its really a moot point to get one unless u already had a nice 990 setup where you could just drop it in from an X6.

Erm, it doesn't...It beats the i5 in a lot of non-gaming tasks. You do know that you can do stuff other that gaming that is highly CPU dependent? I'm sick of people assuming gaming is the be all, end all of high performance computing.
Quote:
Originally Posted by KyadCK View Post

Quote:
Originally Posted by dlee7283 View Post

I think the problem with Piledriver is that it gives performance enthusiasts were already use to in 2009. Its really a moot point to get one unless u already had a nice 990 setup where you could just drop it in from an X6.

I don't think anyone knew the i7 920 would age as well as it did or that the 970 would beat an AMD flagship processor more than 3 years later. The 920 is still better at 4ghz in multi card setups which is even more amazing showing Intel finally got back to where they needed to be.

That said I still like the 8350/20 and think they are good for the performance you get for the price and if you intend just to run one card. My main qualm is AMD's chipsets which I see as the real problem as the current IB ones blows the 990 out of the water.

Quick question for you here.

990FX allows for 32GB of addressable ram. It gives out 40ish PCI-e lanes, and comes with 6 SATA3 ports stock. It can do full x8/x8/x8/x8.

Piledriver fixed a large number of multi-GPU issues, which means it was the CPU, not the chipset.

So knowing this, what exactly is bad about the chipset? I hear all these complaints about it, but they all boil down to "it;'s bad for multi-gpu", which is bull since if it was the chipset, PD couldn't have done any better then BD, but it did. (and yes, the 8150 and 8350 both have a 2.6Ghz HyperTransport)

The SATA controller is slower than Intels, admittedly that doesn't create much of a difference but my boot time was noticeably faster on my laptop with a P55m chipset than on my SB950 based one.

The dual card bottleneck certainly wasn't the CPU as such, although PD fixing it makes me believe it may have been on the CPU side but not the actual cores performance, as in it's on the CPU/NB and related to how the HT link talks to the CPU or something...Admittedly, it doesn't make a difference to anyone. Proof being that I know someone who only gained ~2fps when he added a second GTX 480 that was fixed on Intel, but cards faster than a GTX 480 + 2fps were still faster which eliminates the chance of a CPU bottleneck.
Quote:
Originally Posted by tpi2007 View Post

Why would you say that he has that misconception ? I didn't understand that, I think he has the right idea. The problem is that AMD's platforms have the PCIe controller on the Northbridge, which is not only outside the CPU, it is linked to it by an outdated link called HyperTransport.

X58 used the same setup and was a lot faster than 775 or AM2/AM2+/AM3 in dual GPU performance, FM2 uses the PCIe controller on the CPU and isn't any faster than AM3+ for multi-GPU stuff...So yeah, it has nothing to do with HTT.
    
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