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[WCCF]AMD To Launch Richland APUs on 19th March – Piledriver FX CPU Refresh Expected in June 2013 - Page 4

post #31 of 83
My guess is AMD had to whip up something quick, since Steamroller will be released so late. I'm all for performance bumps when they come at the same price point though.
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post #32 of 83
Quote:
Originally Posted by ComputerRestore View Post

So reduce the pipelines a bit to increase IPC which will lower the max frequency to something reasonable 5Ghz-5.5Ghz max, because the platform AM3+ can't handle an 8 core CPU that's meant to run 6Ghz+ on air.

Changing the number of pipeline stages is a major architectural shift, and I doubt even Steamroller will make any significant changes in this regard.
Quote:
Originally Posted by ZealotKi11er View Post

Nothing wrong with updating the lineup.

Indeed.

However, people expecting something more than a clock speed bump are probably fooling themselves.
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post #33 of 83
Quote:
Originally Posted by ComputerRestore View Post

Can't wait to see what changes since:

Piledriver is just a 2nd Gen Bulldozer and with such small tweaks it gave huge improvements.
  • If RCM is going to be introduced, from what I've read, it can be engineered to work at any range - i.e. 4.0Ghz-4.5Ghz [But is less effective out of that range by %+- from optimal range]
  • These CPU's use so little power at low frequencies (Example: FX8350 @ 3.5Ghz 1.2v 85W)
  • So maybe with RCM it could be something like this? FX 8450 3.5Ghz - Turbo 4.5Ghz 95W 32nm

RCM aside (cause it probably wont be on this revision) it will be interesting to see what else they can do, with the Module design to really push these chips.
My thoughts:
- shorter pipelines: why? I'd say this design is capable of 6Ghz+ on air but....
  • AM3+ motherboards struggle with proper power delivery at that frequency, unless sub-zero
  • communication through the silicon becomes unstable at those frequencies unless cooled (sub 20C)
  • temperatures become too high to maintain stability

So reduce the pipelines a bit to increase IPC which will lower the max frequency to something reasonable 5Ghz-5.5Ghz max, because the platform AM3+ can't handle an 8 core CPU that's meant to run 6Ghz+ on air.

Except they're switching off AM3+ after SR anyway, and I'd rather them keep it long but work on ways to reduce the penalty for branch misprediction, etc...Work on the negatives so you can keep the positives.
Quote:
Originally Posted by Purger View Post

My guess is AMD had to whip up something quick, since Steamroller will be released so late. I'm all for performance bumps when they come at the same price point though.

It's entirely possible that like the first Bulldozer, this could be what they've done so far released in order to have a product on the market.
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post #34 of 83
Quote:
Originally Posted by Brutuz View Post

Except they're switching off AM3+ after SR anyway, and I'd rather them keep it long but work on ways to reduce the penalty for branch misprediction, etc...Work on the negatives so you can keep the positives.

Good point.
Although it makes me wonder, why, if they could just take the easy way out, that they don't.

Is it possible they already have it figured out? Will it be a revolutionary leap?
post #35 of 83
Quote:
Originally Posted by ComputerRestore View Post

Quote:
Originally Posted by Brutuz View Post

Except they're switching off AM3+ after SR anyway, and I'd rather them keep it long but work on ways to reduce the penalty for branch misprediction, etc...Work on the negatives so you can keep the positives.

Good point.
Although it makes me wonder, why, if they could just take the easy way out, that they don't.

Is it possible they already have it figured out? Will it be a revolutionary leap?

The pipeline in SB/IB is actually fairly long, it's no-where near a Pentium 4 or Bulldozer but it's very long still, Intel have managed to ensure that it can be much shorter in as many scenarios as possible so clock speeds still go high but IPC remains high, I'd imagine AMD is mainly trying to work on that and power consumption.
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post #36 of 83
Intel has a far superior branch prediction front end, and the advantage of the micro-op cache.

So far from what I've read from Anandtech, Steamroller's integer cores are going to be the exact same as Bulldozer, or at least very similar. The biggest changes are at the front end, and on the FPU unit, as well as some L2 power saving tweaks. L3 high latency problems aren't going to be addressed until Excavator.

As for the big front end changes, it will be implementation of something similar to Intel's micro-op cache, and an independent decoder per core. Branch prediction should also be improved.

If I recall correctly, IB and SB's pipeline length was somewhere around 16 to 19, while Bulldozer is in the low 20s. P4 was 28-39, depending on generation. Whenever Bulldozer suffered a branch misprediction, it lost somewhere around 20-30 cycles. SB on the other hand only suffers 14-17, 14 if the instructions are still in the micro-op cache, 17 if it needs to retrieve data from the L1 cache. P4's branch misprediction penalty was 20 to over 100 cycles.

Here is Anand's good in-depth article.
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post #37 of 83
Quote:
Originally Posted by Tsumi View Post

Intel has a far superior branch prediction front end, and the advantage of the micro-op cache.

So far from what I've read from Anandtech, Steamroller's integer cores are going to be the exact same as Bulldozer, or at least very similar. The biggest changes are at the front end, and on the FPU unit, as well as some L2 power saving tweaks. L3 high latency problems aren't going to be addressed until Excavator.

As for the big front end changes, it will be implementation of something similar to Intel's micro-op cache, and an independent decoder per core. Branch prediction should also be improved.

If I recall correctly, IB and SB's pipeline length was somewhere around 16 to 19, while Bulldozer is in the low 20s. P4 was 28-39, depending on generation. Whenever Bulldozer suffered a branch misprediction, it lost somewhere around 20-30 cycles. SB on the other hand only suffers 14-17, 14 if the instructions are still in the micro-op cache, 17 if it needs to retrieve data from the L1 cache. P4's branch misprediction penalty was 20 to over 100 cycles.

Here is Anand's good in-depth article.

Very nice article.

So with the Bulldozer design being built around parallelism and fast recovery from mispredictions, maybe once it's been perfected we can see:
- Single Threaded code processed over a module instead of a core (2X the speed of current Bulldozer IPC on single threaded code)
- Even faster and more effecient multithreaded performance

?? - Discuss?
post #38 of 83
Quote:
Originally Posted by ComputerRestore View Post

- Single Threaded code processed over a module instead of a core (2X the speed of current Bulldozer IPC on single threaded code)

No. A module is more than just a super wide single core, it has significant components that are largely independent, and the same sort of coherency issues that make "reverse hyperthreading" impossible will keep all the resources in a module from being devoted to a single thread/logical CPU.

I suppose it would be possible to make one enormously wide (8-issue) core, then split it up as needed with SMT, but it's very hard to take advantage of that kind of instruction level parallelism, and SMT has some significant overhead issues in certain scenarios. I don't see AMD going this route as it would be a total reversal of what they have been doing, and it would sacrifice significant multi-threaded performance for a moderate single thread boost, which won't serve their interests in the long run.
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post #39 of 83
Quote:
Originally Posted by Blameless View Post

No. A module is more than just a super wide single core, it has significant components that are largely independent, and the same sort of coherency issues that make "reverse hyperthreading" impossible will keep all the resources in a module from being devoted to a single thread/logical CPU.

I suppose it would be possible to make one enormously wide (8-issue) core, then split it up as needed with SMT, but it's very hard to take advantage of that kind of instruction level parallelism, and SMT has some significant overhead issues in certain scenarios. I don't see AMD going this route as it would be a total reversal of what they have been doing, and it would sacrifice significant multi-threaded performance for a moderate single thread boost, which won't serve their interests in the long run.

That's kind of what I was thinking. Since they don't yet have the full NB integrated onto the CPU could it be possible to:
1) Design the rest of the NB components into a hardware level scheduler independent of the OS to control threading.(i.e.Move a single thread across 2 Modules)
2) Would that design bottleneck the multithreaded ability of the CPU (could a single scheduler keep up with 8 Cores/4 Modules)

It just makes me think of the PS3 CPU design.
post #40 of 83
Quote:
Originally Posted by ComputerRestore View Post

Quote:
Originally Posted by Blameless View Post

No. A module is more than just a super wide single core, it has significant components that are largely independent, and the same sort of coherency issues that make "reverse hyperthreading" impossible will keep all the resources in a module from being devoted to a single thread/logical CPU.

I suppose it would be possible to make one enormously wide (8-issue) core, then split it up as needed with SMT, but it's very hard to take advantage of that kind of instruction level parallelism, and SMT has some significant overhead issues in certain scenarios. I don't see AMD going this route as it would be a total reversal of what they have been doing, and it would sacrifice significant multi-threaded performance for a moderate single thread boost, which won't serve their interests in the long run.

That's kind of what I was thinking. Since they don't yet have the full NB integrated onto the CPU could it be possible to:
1) Design the rest of the NB components into a hardware level scheduler independent of the OS to control threading.(i.e.Move a single thread across 2 Modules)
2) Would that design bottleneck the multithreaded ability of the CPU (could a single scheduler keep up with 8 Cores/4 Modules)

It just makes me think of the PS3 CPU design.

Uh.... the Northbridge has nothing at all to do with any CPU related task. It's a switch designed to talk to HyperTransport, and everything on the motherboard that isn't RAM. (Southbridge, back IO pannel, expansion slots, etc) and to support virtual addressing of those connections (IOMMU).

Also, switching threads between 2 cores is a bad idea. If you run at 4Ghz, no matter how many cores you have, you have only 4Ghz worth of time. Why waste time moving things to a different core? Run 2 billion cycles here, move it, run 2 billion there... why? You don't gain anything at all.
Edited by KyadCK - 2/7/13 at 9:26am
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64GB Corsair Dominator Platinum (3000Mhz 8x8GB) Samsung 950 Pro NVMe 512GB EK Predator 240 Windows 10 Enterprise x64 
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2x Acer XR341CK Corsair Vengeance K70 RGB Corsair AX1200 Corsair Graphite 780T 
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30ART Mic Tube Amp 
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Overclock.net › Forums › Industry News › Rumors and Unconfirmed Articles › [WCCF]AMD To Launch Richland APUs on 19th March – Piledriver FX CPU Refresh Expected in June 2013